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[83.9.2.24]) by smtp.gmail.com with ESMTPSA id f6-20020a17090631c600b008779b5c7db6sm5411656ejf.107.2023.01.23.08.26.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jan 2023 08:26:25 -0800 (PST) Message-ID: <2f0881e3-9f6c-1c77-c6ca-3e291b37bd12@linaro.org> Date: Mon, 23 Jan 2023 17:26:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v4 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible Content-Language: en-US To: Luca Weiss , Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold References: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> <20230120-sm6350-usbphy-v4-3-4d700a90ba16@fairphone.com> From: Konrad Dybcio In-Reply-To: <20230120-sm6350-usbphy-v4-3-4d700a90ba16@fairphone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.01.2023 14:29, Luca Weiss wrote: > The sc7180 phy compatible works fine for some cases, but it turns out > sm6350 does need proper phy configuration in the driver, so use the > newly added sm6350 compatible. > > Because the sm6350 compatible is using the new binding, we need to > change the node quite a bit to match it. > > This fixes qmpphy init when no USB cable is plugged in during bootloader > stage. > > Reviewed-by: Johan Hovold > Signed-off-by: Luca Weiss > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sm6350.dtsi | 54 +++++++++++------------------------- > 1 file changed, 16 insertions(+), 38 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 8224adb99948..128dbbe23ef5 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -1314,49 +1315,26 @@ usb_1_hsphy: phy@88e3000 { > resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > }; > > - usb_1_qmpphy: phy@88e9000 { > - compatible = "qcom,sc7180-qmp-usb3-dp-phy"; > - reg = <0 0x088e9000 0 0x200>, > - <0 0x088e8000 0 0x40>, > - <0 0x088ea000 0 0x200>; > - status = "disabled"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + usb_1_qmpphy: phy@88e8000 { > + compatible = "qcom,sm6350-qmp-usb3-dp-phy"; > + reg = <0 0x088e8000 0 0x3000>; > > clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > - <&xo_board>, > - <&rpmhcc RPMH_QLINK_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > > - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > - <&gcc GCC_USB3_PHY_PRIM_BCR>; > + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; > reset-names = "phy", "common"; > > - usb_1_ssphy: usb3-phy@88e9200 { > - reg = <0 0x088e9200 0 0x200>, > - <0 0x088e9400 0 0x200>, > - <0 0x088e9c00 0 0x400>, > - <0 0x088e9600 0 0x200>, > - <0 0x088e9800 0 0x200>, > - <0 0x088e9a00 0 0x100>; > - #clock-cells = <0>; > - #phy-cells = <0>; > - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > - clock-names = "pipe0"; > - clock-output-names = "usb3_phy_pipe_clk_src"; > - }; > + #clock-cells = <1>; > + #phy-cells = <1>; > > - dp_phy: dp-phy@88ea200 { > - reg = <0 0x088ea200 0 0x200>, > - <0 0x088ea400 0 0x200>, > - <0 0x088eaa00 0 0x200>, > - <0 0x088ea600 0 0x200>, > - <0 0x088ea800 0 0x200>; > - #phy-cells = <0>; > - #clock-cells = <1>; > - }; > + status = "disabled"; > }; > > dc_noc: interconnect@9160000 { > @@ -1430,7 +1408,7 @@ usb_1_dwc3: usb@a600000 { > snps,dis_enblslpm_quirk; > snps,has-lpm-erratum; > snps,hird-threshold = /bits/ 8 <0x10>; > - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; > phy-names = "usb2-phy", "usb3-phy"; > }; > }; >