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From: Tom Lendacky <thomas.lendacky@amd.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	x86@kernel.org, tglx@linutronix.de, andrew.cooper3@citrix.com,
	"Ingo Molnar" <mingo@redhat.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>,
	"Joerg Roedel" <joro@8bytes.org>, "Borislav Petkov" <bp@suse.de>,
	"David Woodhouse" <dwmw@amazon.co.uk>,
	"Janakarajan Natarajan" <Janakarajan.Natarajan@amd.com>,
	"Kees Cook" <keescook@chromium.org>,
	"KarimAllah Ahmed" <karahmed@amazon.de>,
	"Andy Lutomirski" <luto@kernel.org>
Subject: Re: [PATCH v1 2/3] x86/bugs: Add AMD's SPEC_CTRL MSR usage
Date: Mon, 4 Jun 2018 15:43:17 -0500	[thread overview]
Message-ID: <2f325eea-5ffc-70f5-43d8-59ceef73d04d@amd.com> (raw)
In-Reply-To: <20180604202024.GF5867@char.us.oracle.com>

On 6/4/2018 3:20 PM, Konrad Rzeszutek Wilk wrote:
>>> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>>> index 26110c202b19..950ec50f77c3 100644
>>> --- a/arch/x86/kvm/svm.c
>>> +++ b/arch/x86/kvm/svm.c
>>> @@ -4115,7 +4115,8 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>>>  		break;
>>>  	case MSR_IA32_SPEC_CTRL:
>>>  		if (!msr_info->host_initiated &&
>>> -		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
>>> +		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
>>> +		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
>>
>> Shouldn't the IBRS/SSBD check be an "or" check?  I don't think it's
>> necessarily true that IBRS and SSBD have to both be set.  Maybe something
>> like:
>>
>> 	if (!msr_info->host_initiated &&
>> 	    !(guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) ||
>> 	      guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
>>
>> Does that make sense?
> 
> The '!' on each of the CPUID and '&&' make this the same. See:

Doh!  Yes, I don't know what I was thinking.  Just the end of a long
week I guess.

> 
> 
>  AMD_IBRS set	|  AMD_SSBD set	| !AMD_IBRS && !AMD_SSBD | !(AMD_IBRS || AMD_SSBD)
> 	0	|	0	| 1 && 1 -> return 1	 | !(0) -> 1 -> return 1
> 	1	|	0	| 0 && 1, continue	 | !(1 || 0) -> continue
> 	1	|	1	| 0 && 0, continue	 | !(1 || 1) -> continue
> 	0	|	1	| 1 && 0, continue	 | !(0 || 1) -> continue
> 
> Meaning we will return 1 if:
>  the host has not initiator it or,
>  the guest CPUID does not have AMD_IBRS flag or,
>  the guest CPUID does not have AMD SSBD flag
> 
> I am fine modifying it the way you had in mind, but in the past the logic
> was to use ! and &&, hence stuck to that.

No reason to change, it's fine the way you have it.

Thanks,
Tom

>>
>>>  			return 1;
>>>  
>>>  		msr_info->data = svm->spec_ctrl;
>>> @@ -4217,11 +4218,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
>>>  		break;
>>>  	case MSR_IA32_SPEC_CTRL:
>>>  		if (!msr->host_initiated &&
>>> -		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
>>> +		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
>>> +		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
>>
>> Same question as above.
>>
>> Thanks,
>> Tom
>>
>>>  			return 1;
>>>  
>>>  		/* The STIBP bit doesn't fault even if it's not advertised */
>>> -		if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
>>> +		if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
>>>  			return 1;
>>>  
>>>  		svm->spec_ctrl = data;
>>>

  reply	other threads:[~2018-06-04 20:43 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-01 14:59 [PATCH v1] AMD SSB bits Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 1/3] x86/bugs: Add AMD's variant of SSB_NO Konrad Rzeszutek Wilk
2018-06-06 12:15   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 2/3] x86/bugs: Add AMD's SPEC_CTRL MSR usage Konrad Rzeszutek Wilk
2018-06-02  1:04   ` Tom Lendacky
2018-06-04 20:20     ` Konrad Rzeszutek Wilk
2018-06-04 20:43       ` Tom Lendacky [this message]
2018-06-04 20:54         ` Konrad Rzeszutek Wilk
2018-06-06 12:16   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 3/3] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features Konrad Rzeszutek Wilk
2018-06-06 12:16   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-08 21:30   ` [PATCH v1 3/3] " Tom Lendacky
2018-06-11 14:01     ` Konrad Rzeszutek Wilk
2018-06-12 14:38       ` Tom Lendacky
2018-06-15 18:57         ` Thomas Gleixner
2018-06-15 19:38           ` Konrad Rzeszutek Wilk
2018-06-05 13:23 ` [PATCH v1] AMD SSB bits Tom Lendacky
2018-06-05 20:56   ` Konrad Rzeszutek Wilk

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