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From: "Michał Mirosław" <>
To: Ulf Hansson <>,
	Kevin Liu <>,
	Suneel Garapati <>
Cc: Adrian Hunter <>,
	Chris Ball <>,,,,
	Michal Simek <>
Subject: [PATCH v3 1/5] mmc: sdhci: fix base clock usage in preset value
Date: Sun, 25 Jul 2021 06:25:16 +0200	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read
is overwritten for programmable clock preset, but is carried over for
divided clock preset. This can confuse sdhci_enable_clk() if the register
has enable bits set for some reason at time time of clock calculation.
Remove the read.

Quoting Al Cooper:

sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always
return the divider value without the enable set, so this fixes a case
for DDR52 where the enable was not being cleared when the divider
value was changed.

Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function")
Signed-off-by: Michał Mirosław <>
Acked-by: Al Cooper <>

v3: updated commit message
v2: removed truncated sentence from commitmsg

Signed-off-by: Michał Mirosław <>
 drivers/mmc/host/sdhci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index aba6e10b8605..c7438dd13e3e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1857,7 +1857,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 		if (host->preset_enabled) {
 			u16 pre_val;
-			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 			pre_val = sdhci_get_preset_value(host);
 			if (host->clk_mul &&

  parent reply	other threads:[~2021-07-25  4:25 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <>
2021-07-25  4:25 ` [PATCH v3 3/5] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN Michał Mirosław
2021-07-25  4:25 ` [PATCH v3 2/5] mmc: sdhci: always obey programmable clock config in preset value Michał Mirosław
2021-07-25  4:25 ` Michał Mirosław [this message]
2021-07-25  4:25 ` [PATCH v3 4/5] mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit Michał Mirosław
2021-07-25  9:05   ` kernel test robot
2021-07-25 19:16   ` kernel test robot
2021-07-25  4:25 ` [PATCH v3 5/5] mmc: sdhci: simplify v2/v3+ clock calculation Michał Mirosław

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