From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751527AbdG0BCf (ORCPT ); Wed, 26 Jul 2017 21:02:35 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:10354 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751103AbdG0BCd (ORCPT ); Wed, 26 Jul 2017 21:02:33 -0400 Subject: Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported To: Casey Leedom , Alexander Duyck References: <1499955692-26556-1-git-send-email-dingtianhong@huawei.com> <1499955692-26556-3-git-send-email-dingtianhong@huawei.com> <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> <67be791f-e0cf-8284-9229-17174dc741ef@codeaurora.org> <5f9b8bfb-41a8-a17c-6fea-581aec1d5573@huawei.com> <20170724090516.2e0f0d2a@w520.home> CC: Netdev , Bjorn Helgaas , "linux-arm-kernel@lists.infradead.org" , "David.Laight@aculab.com" , "ashok.raj@intel.com" , "Alex Williamson" , "l.stach@pengutronix.de" , "Suravee.Suthikulpanit@amd.com" , "catalin.marinas@arm.com" , "linux-pci@vger.kernel.org" , "will.deacon@arm.com" , Sinan Kaya , "robin.murphy@arm.com" , "linux-kernel@vger.kernel.org" , "davem@davemloft.net" , Ganesh GR , "asit.k.mallick@intel.com" , "jeffrey.t.kirsher@intel.com" , "mark.rutland@arm.com" , "gabriele.paoloni@huawei.com" , Michael Werner , "bhelgaas@google.com" , "patrick.j.cramer@intel.com" , "linuxarm@huawei.com" , "amira@mellanox.com" , "Bob.Shaw@amd.com" From: Ding Tianhong Message-ID: <2feff1a5-25b7-eb6c-7628-7c2257c56e95@huawei.com> Date: Thu, 27 Jul 2017 09:01:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59793B8F.009C,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2a842aec291d72bd811839de189ab591 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2017/7/27 3:05, Casey Leedom wrote: > | From: Alexander Duyck > | Sent: Wednesday, July 26, 2017 11:44 AM > | > | On Jul 26, 2017 11:26 AM, "Casey Leedom" wrote: > | | > | | I think that the patch will need to be extended to modify > | | drivers/pci.c/iov.c:sriov_enable() to explicitly turn off > | | Relaxed Ordering Enable if the Root Complex is marked > | for no RO TLPs. > | > | I'm not sure that would be an issue. Wouldn't most VFs inherit the PF's settings? > > Ah yes, you're right. This is covered in section 3.5.4 of the Single Root I/O > Virtualization and Sharing Specification, Revision 1.0 (September 11, 2007), > governing the PCIe Capability Device Control register. It states that the VF > version of that register shall follow the setting of the corresponding PF. > > So we should enhance the cxgb4vf/sge.c:t4vf_sge_alloc_rxq() in the same > way we did for the cxgb4 driver, but that's not critical since the Relaxed > Ordering Enable supersedes the internal chip's desire to use the Relaxed > Ordering Attribute. > > Ding, send me a note if you'd like me to work that up for you. > Ok, you could send the change log and I could put it in the v8 version together, will you base on the patch 3/3 or build a independence patch? Ding > | Also I thought most of the VF configuration space is read only. > > Yes, but not all of it. And when a VF is exported to a Virtual Machine, > then the Hypervisor captures and interprets all accesses to the VF's > PCIe Configuration Space from the VM. > > Thanks again for reminding me of the subtle aspect of the SR_IOV > specification that I forgot. > > Casey > . >