From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C56C55179 for ; Sun, 25 Oct 2020 07:48:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A8071207BB for ; Sun, 25 Oct 2020 07:48:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1767836AbgJYHsO (ORCPT ); Sun, 25 Oct 2020 03:48:14 -0400 Received: from mailoutvs39.siol.net ([185.57.226.230]:34196 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1765977AbgJYHsN (ORCPT ); Sun, 25 Oct 2020 03:48:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTP id 24D3652ABB8; Sun, 25 Oct 2020 08:48:11 +0100 (CET) X-Virus-Scanned: amavisd-new at psrvmta12.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id JnqKbIAQjfG6; Sun, 25 Oct 2020 08:48:10 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTPS id D5BA352ABC8; Sun, 25 Oct 2020 08:48:10 +0100 (CET) Received: from kista.localnet (cpe1-5-97.cable.triera.net [213.161.5.97]) (Authenticated sender: jernej.skrabec@siol.net) by mail.siol.net (Zimbra) with ESMTPA id 7E43E52ABB8; Sun, 25 Oct 2020 08:48:09 +0100 (CET) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Maxime Ripard , Chen-Yu Tsai Cc: linux-sunxi@googlegroups.com, Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 05/10] ARM: dts: sun8i: h3: orangepi-plus2e: Enable RGMII RX/TX delay on Ethernet PHY Date: Sun, 25 Oct 2020 08:53:39 +0100 Message-ID: <30257881.11H8UbXcPh@kista> In-Reply-To: <20201024162515.30032-5-wens@kernel.org> References: <20201024162515.30032-1-wens@kernel.org> <20201024162515.30032-5-wens@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dne sobota, 24. oktober 2020 ob 18:25:10 CET je Chen-Yu Tsai napisal(a): > From: Chen-Yu Tsai > > The Ethernet PHY on the Orange Pi Plus 2E has the RX and TX delays > enabled on the PHY, using pull-ups on the RXDLY and TXDLY pins. > > Fix the phy-mode description to correct reflect this so that the > implementation doesn't reconfigure the delays incorrectly. This > happened with commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e > rx/tx delay config"). > > Fixes: 4904337fe34f ("ARM: dts: sunxi: Restore EMAC changes (boards)") > Fixes: 7a78ef92cdc5 ("ARM: sun8i: h3: Enable EMAC with external PHY on Orange Pi Plus 2E") > Signed-off-by: Chen-Yu Tsai Tested-by: Jernej Skrabec Acked-by: Jernej Skrabec Best regards, Jernej