From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: Vidya Sagar <vidyas@nvidia.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
"jonathanh@nvidia.com" <jonathanh@nvidia.com>,
"kishon@ti.com" <kishon@ti.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>
Cc: "mperttunen@nvidia.com" <mperttunen@nvidia.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kthota@nvidia.com" <kthota@nvidia.com>,
"mmaddireddy@nvidia.com" <mmaddireddy@nvidia.com>,
"sagar.tv@gmail.com" <sagar.tv@gmail.com>
Subject: RE: [PATCH V3 06/16] PCI: dwc: Add ext config space capability search API
Date: Wed, 17 Apr 2019 09:27:59 +0000 [thread overview]
Message-ID: <305100E33629484CBB767107E4246BBB0A22C0A7@de02wembxa.internal.synopsys.com> (raw)
In-Reply-To: <20190416192730.15681-7-vidyas@nvidia.com>
On Tue, Apr 16, 2019 at 20:27:20, Vidya Sagar <vidyas@nvidia.com> wrote:
> Add extended configuration space capability search API using struct dw_pcie *
> pointer
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes from [v2]:
> * None
>
> Changes from [v1]:
> * This is a new patch in v2 series
>
> drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 42 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index d68c123e409c..44c0ba078452 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
> return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
> }
>
> +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
> + int cap)
> +{
> + u32 header;
> + int ttl;
> + int pos = PCI_CFG_SPACE_SIZE;
> +
> + /* minimum 8 bytes per capability */
> + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
> +
> + if (start)
> + pos = start;
> +
> + header = dw_pcie_readl_dbi(pci, pos);
> + /*
> + * If we have no capabilities, this is indicated by cap ID,
> + * cap version and next pointer all being 0.
> + */
> + if (header == 0)
> + return 0;
> +
> + while (ttl-- > 0) {
> + if (PCI_EXT_CAP_ID(header) == cap && pos != start)
> + return pos;
> +
> + pos = PCI_EXT_CAP_NEXT(header);
> + if (pos < PCI_CFG_SPACE_SIZE)
> + break;
> +
> + header = dw_pcie_readl_dbi(pci, pos);
> + }
> +
> + return 0;
> +}
> +
> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
> +{
> + return dw_pcie_find_next_ext_capability(pci, 0, cap);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
> +
> int dw_pcie_read(void __iomem *addr, int size, u32 *val)
> {
> if (!IS_ALIGNED((uintptr_t)addr, size)) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 4ccd4c706ddb..fa41d675c48f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -248,6 +248,7 @@ struct dw_pcie {
> container_of((endpoint), struct dw_pcie, ep)
>
> u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
>
> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> int dw_pcie_write(void __iomem *addr, int size, u32 val);
> --
> 2.17.1
This ext capability function is aimed to be used by the EP also?
next prev parent reply other threads:[~2019-04-17 9:28 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-16 19:27 [PATCH V3 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 01/16] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 02/16] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-04-17 9:56 ` Gustavo Pimentel
2019-04-22 7:54 ` Jisheng Zhang
2019-04-23 6:11 ` Vidya Sagar
2019-04-23 9:40 ` Gustavo Pimentel
2019-04-30 0:36 ` [EXT] " Z.q. Hou
2019-04-16 19:27 ` [PATCH V3 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-17 9:28 ` Gustavo Pimentel
2019-04-16 19:27 ` [PATCH V3 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-17 9:27 ` Gustavo Pimentel [this message]
2019-04-17 9:34 ` Vidya Sagar
2019-04-17 9:46 ` Gustavo Pimentel
2019-04-16 19:27 ` [PATCH V3 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-17 9:39 ` Gustavo Pimentel
2019-04-16 19:27 ` [PATCH V3 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-04-16 19:27 ` [PATCH V3 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=305100E33629484CBB767107E4246BBB0A22C0A7@de02wembxa.internal.synopsys.com \
--to=gustavo.pimentel@synopsys.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=jingoohan1@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=kishon@ti.com \
--cc=kthota@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=mperttunen@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sagar.tv@gmail.com \
--cc=thierry.reding@gmail.com \
--cc=vidyas@nvidia.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).