From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A02CBC432BE for ; Wed, 28 Jul 2021 21:17:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 800E7600CD for ; Wed, 28 Jul 2021 21:17:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231825AbhG1VRr (ORCPT ); Wed, 28 Jul 2021 17:17:47 -0400 Received: from gloria.sntech.de ([185.11.138.130]:53666 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231755AbhG1VRq (ORCPT ); Wed, 28 Jul 2021 17:17:46 -0400 Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m8qvj-00086Y-Gz; Wed, 28 Jul 2021 23:17:31 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Rob Herring , Peter Geis , cl@rock-chips.com, kever.yang@rock-chips.com Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/8] arm64: dts: rockchip: add rk3568 tsadc nodes Date: Wed, 28 Jul 2021 23:17:30 +0200 Message-ID: <3091522.BEx9A2HvPv@diego> In-Reply-To: <20210728180034.717953-6-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> <20210728180034.717953-6-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, Kever, Am Mittwoch, 28. Juli 2021, 20:00:31 CEST schrieb Peter Geis: > Add the thermal and tsadc nodes to the rk3568 device tree. > There are two sensors, one for the cpu, one for the gpu. > > Signed-off-by: Peter Geis > --- > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 7 ++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++ > 2 files changed, 77 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > index a588ca95ace2..3b1efaf2646e 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > @@ -2420,6 +2420,13 @@ spi3m1_cs1: spi3m1-cs1 { > }; > > tsadc { > + /omit-if-no-ref/ > + tsadc_pin: tsadc-pin { > + rockchip,pins = > + /* tsadc_pin */ > + <0 RK_PA1 0 &pcfg_pull_none>; > + }; > + The rk3568-pinctrl.dtsi is autogenerated on Rockchip's side and I don't want to break that unnecessarily ;-) . So the question below is more for Kever and Liang: The tsadc on most mainline Rockchip socs uses the additional init-pinctrl to set the pin to gpio mode before the tsadc probes and only to the shutdown function after the tsadc has probed sucessfully. This prevents the shutdown firing before the tsadc actually attached to the pin function. Is it possible to fit the above addition pin setting in the database you have as base for the autogeneration? Thanks Heiko > /omit-if-no-ref/ > tsadcm0_shut: tsadcm0-shut { > rockchip,pins = > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index fbd9f1c366ff..c74072941da1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -50,6 +50,7 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > clocks = <&scmi_clk 0>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -58,6 +59,7 @@ cpu1: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -66,6 +68,7 @@ cpu2: cpu@200 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -74,6 +77,7 @@ cpu3: cpu@300 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -773,6 +777,72 @@ uart9: serial@fe6d0000 { > status = "disabled"; > }; > > + thermal_zones: thermal-zones { > + cpu_thermal: cpu-thermal { > + polling-delay-passive = <100>; > + polling-delay = <1000>; > + > + thermal-sensors = <&tsadc 0>; > + > + trips { > + cpu_alert0: cpu_alert0 { > + temperature = <70000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_alert1: cpu_alert1 { > + temperature = <75000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_crit: cpu_crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&cpu_alert0>; > + cooling-device = > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + gpu_thermal: gpu-thermal { > + polling-delay-passive = <20>; /* milliseconds */ > + polling-delay = <1000>; /* milliseconds */ > + > + thermal-sensors = <&tsadc 1>; > + }; > + }; > + > + tsadc: tsadc@fe710000 { > + compatible = "rockchip,rk3568-tsadc"; > + reg = <0x0 0xfe710000 0x0 0x100>; > + interrupts = ; > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > + assigned-clock-rates = <17000000>, <700000>; > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > + clock-names = "tsadc", "apb_pclk"; > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > + <&cru SRST_TSADCPHY>; > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > + rockchip,grf = <&grf>; > + rockchip,hw-tshut-temp = <95000>; > + pinctrl-names = "init", "default", "sleep"; > + pinctrl-0 = <&tsadc_pin>; > + pinctrl-1 = <&tsadc_shutorg>; > + pinctrl-2 = <&tsadc_pin>; > + #thermal-sensor-cells = <1>; > + status = "disabled"; > + }; > + > saradc: saradc@fe720000 { > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > reg = <0x0 0xfe720000 0x0 0x100>; >