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* [PATCH 0/2] arm64: dts: ti: k3-j7200-som/cpb: Correct i2c bus representations
@ 2020-11-19 13:26 Peter Ujfalusi
  2020-11-19 13:26 ` [PATCH 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM Peter Ujfalusi
  2020-11-19 13:26 ` [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 Peter Ujfalusi
  0 siblings, 2 replies; 6+ messages in thread
From: Peter Ujfalusi @ 2020-11-19 13:26 UTC (permalink / raw)
  To: nm, t-kristo
  Cc: linux-arm-kernel, linux-kernel, devicetree, nsekhar, vigneshr

Hi,

The main_i2c0 missed the ioexpander present on the SOM itself to control muxes
to route signals to CPB connectors.

The main_i2c1 of J7200 is _not_ connected to the i2c1 of CPB, it is connected to
i2c3, so the devices on the CPB's i2c1 bus are not avalible, but the ones on the
CPB i2c3 are available under the main_i2c1.

Add nice line names at the same time to these.

Regards,
Peter
---
Peter Ujfalusi (2):
  arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the
    SOM
  arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io
    expander on main_i2c1

 .../dts/ti/k3-j7200-common-proc-board.dts     | 16 +++---------
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   | 26 +++++++++++++++++++
 2 files changed, 30 insertions(+), 12 deletions(-)

-- 
Peter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM
  2020-11-19 13:26 [PATCH 0/2] arm64: dts: ti: k3-j7200-som/cpb: Correct i2c bus representations Peter Ujfalusi
@ 2020-11-19 13:26 ` Peter Ujfalusi
  2020-11-19 14:45   ` Vignesh Raghavendra
  2020-11-19 13:26 ` [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 Peter Ujfalusi
  1 sibling, 1 reply; 6+ messages in thread
From: Peter Ujfalusi @ 2020-11-19 13:26 UTC (permalink / raw)
  To: nm, t-kristo
  Cc: linux-arm-kernel, linux-kernel, devicetree, nsekhar, vigneshr

It is used to control several SOM level muxes to make sure that the correct
signals are routed to the correct pin on the SOM <-> CPB connectors.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 .../dts/ti/k3-j7200-common-proc-board.dts     | 11 --------
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   | 26 +++++++++++++++++++
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6b3863108571..2721137d8943 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -43,13 +43,6 @@ J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
 };
 
 &main_pmx0 {
-	main_i2c0_pins_default: main-i2c0-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
-			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
-		>;
-	};
-
 	main_i2c1_pins_default: main-i2c1-pins-default {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
@@ -146,10 +139,6 @@ &cpsw_port1 {
 };
 
 &main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
 	exp1: gpio@20 {
 		compatible = "ti,tca6416";
 		reg = <0x20>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index fbd17d38f6b6..7b5e9aa0324e 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -48,6 +48,15 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
 	};
 };
 
+&main_pmx0 {
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
+			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
+		>;
+	};
+};
+
 &hbmc {
 	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
 	 * appropriate node based on board detection
@@ -131,3 +140,20 @@ &mailbox0_cluster10 {
 &mailbox0_cluster11 {
 	status = "disabled";
 };
+
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	exp_som: gpio@21 {
+		compatible = "ti,tca6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
+				  "GPIO_LIN_EN", "CAN_STB";
+	};
+};
-- 
Peter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1
  2020-11-19 13:26 [PATCH 0/2] arm64: dts: ti: k3-j7200-som/cpb: Correct i2c bus representations Peter Ujfalusi
  2020-11-19 13:26 ` [PATCH 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM Peter Ujfalusi
@ 2020-11-19 13:26 ` Peter Ujfalusi
  2020-11-19 16:10   ` Vignesh Raghavendra
  1 sibling, 1 reply; 6+ messages in thread
From: Peter Ujfalusi @ 2020-11-19 13:26 UTC (permalink / raw)
  To: nm, t-kristo
  Cc: linux-arm-kernel, linux-kernel, devicetree, nsekhar, vigneshr

J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3

The i2c1 devices on the CPB are _not_ connected to the SoC, they are not
usable with the J7200 SOM.

Correct the expander name from exp4 to exp3 and at the same time add the
line names as well.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 2721137d8943..83e043c65f81 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -159,11 +159,14 @@ &main_i2c1 {
 	pinctrl-0 = <&main_i2c1_pins_default>;
 	clock-frequency = <400000>;
 
-	exp4: gpio@20 {
+	exp3: gpio@20 {
 		compatible = "ti,tca6408";
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
+				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
+				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
 	};
 };
 
-- 
Peter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM
  2020-11-19 13:26 ` [PATCH 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM Peter Ujfalusi
@ 2020-11-19 14:45   ` Vignesh Raghavendra
  0 siblings, 0 replies; 6+ messages in thread
From: Vignesh Raghavendra @ 2020-11-19 14:45 UTC (permalink / raw)
  To: Peter Ujfalusi, nm, t-kristo
  Cc: linux-arm-kernel, linux-kernel, devicetree, nsekhar



On 11/19/20 6:56 PM, Peter Ujfalusi wrote:
> It is used to control several SOM level muxes to make sure that the correct
> signals are routed to the correct pin on the SOM <-> CPB connectors.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---

Yes, there is indeed a I2C GPIO expander on SOM that's missing from DT
today. So this change looks good to me.

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>

Regards
Vignesh

>  .../dts/ti/k3-j7200-common-proc-board.dts     | 11 --------
>  arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   | 26 +++++++++++++++++++
>  2 files changed, 26 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 6b3863108571..2721137d8943 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -43,13 +43,6 @@ J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>  };
>  
>  &main_pmx0 {
> -	main_i2c0_pins_default: main-i2c0-pins-default {
> -		pinctrl-single,pins = <
> -			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
> -			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
> -		>;
> -	};
> -
>  	main_i2c1_pins_default: main-i2c1-pins-default {
>  		pinctrl-single,pins = <
>  			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
> @@ -146,10 +139,6 @@ &cpsw_port1 {
>  };
>  
>  &main_i2c0 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&main_i2c0_pins_default>;
> -	clock-frequency = <400000>;
> -
>  	exp1: gpio@20 {
>  		compatible = "ti,tca6416";
>  		reg = <0x20>;
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> index fbd17d38f6b6..7b5e9aa0324e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> @@ -48,6 +48,15 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>  	};
>  };
>  
> +&main_pmx0 {
> +	main_i2c0_pins_default: main-i2c0-pins-default {
> +		pinctrl-single,pins = <
> +			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
> +			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
> +		>;
> +	};
> +};
> +
>  &hbmc {
>  	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
>  	 * appropriate node based on board detection
> @@ -131,3 +140,20 @@ &mailbox0_cluster10 {
>  &mailbox0_cluster11 {
>  	status = "disabled";
>  };
> +
> +&main_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_i2c0_pins_default>;
> +	clock-frequency = <400000>;
> +
> +	exp_som: gpio@21 {
> +		compatible = "ti,tca6408";
> +		reg = <0x21>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
> +				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
> +				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
> +				  "GPIO_LIN_EN", "CAN_STB";
> +	};
> +};
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1
  2020-11-19 13:26 ` [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 Peter Ujfalusi
@ 2020-11-19 16:10   ` Vignesh Raghavendra
  2020-11-20  7:07     ` Peter Ujfalusi
  0 siblings, 1 reply; 6+ messages in thread
From: Vignesh Raghavendra @ 2020-11-19 16:10 UTC (permalink / raw)
  To: Peter Ujfalusi, nm, t-kristo
  Cc: linux-arm-kernel, linux-kernel, devicetree, nsekhar



On 11/19/20 6:56 PM, Peter Ujfalusi wrote:
> J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3
> 
> The i2c1 devices on the CPB are _not_ connected to the SoC, they are not
> usable with the J7200 SOM.
> 
> Correct the expander name from exp4 to exp3 and at the same time add the
> line names as well.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---

Yes, the schematics call this expander as exp3. Thanks for the fix

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>

>  arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 2721137d8943..83e043c65f81 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -159,11 +159,14 @@ &main_i2c1 {
>  	pinctrl-0 = <&main_i2c1_pins_default>;
>  	clock-frequency = <400000>;
>  
> -	exp4: gpio@20 {
> +	exp3: gpio@20 {
>  		compatible = "ti,tca6408";
>  		reg = <0x20>;
>  		gpio-controller;
>  		#gpio-cells = <2>;
> +		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
> +				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
> +				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";

I assume these lines have same meaning in J721e and J7200? If so, then
no issues.

>  	};
>  };
>  
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1
  2020-11-19 16:10   ` Vignesh Raghavendra
@ 2020-11-20  7:07     ` Peter Ujfalusi
  0 siblings, 0 replies; 6+ messages in thread
From: Peter Ujfalusi @ 2020-11-20  7:07 UTC (permalink / raw)
  To: Vignesh Raghavendra, nm, t-kristo
  Cc: linux-arm-kernel, linux-kernel, devicetree, nsekhar



On 19/11/2020 18.10, Vignesh Raghavendra wrote:
> 
> 
> On 11/19/20 6:56 PM, Peter Ujfalusi wrote:
>> J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3
>>
>> The i2c1 devices on the CPB are _not_ connected to the SoC, they are not
>> usable with the J7200 SOM.
>>
>> Correct the expander name from exp4 to exp3 and at the same time add the
>> line names as well.
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>> ---
> 
> Yes, the schematics call this expander as exp3. Thanks for the fix

The CPB is the same for both j721e and j7200 SOMs.
I'll send v2 with a small comment block to explain this.

> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
> 
>>  arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>> index 2721137d8943..83e043c65f81 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>> @@ -159,11 +159,14 @@ &main_i2c1 {
>>  	pinctrl-0 = <&main_i2c1_pins_default>;
>>  	clock-frequency = <400000>;
>>  
>> -	exp4: gpio@20 {
>> +	exp3: gpio@20 {
>>  		compatible = "ti,tca6408";
>>  		reg = <0x20>;
>>  		gpio-controller;
>>  		#gpio-cells = <2>;
>> +		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
>> +				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
>> +				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
> 
> I assume these lines have same meaning in J721e and J7200? If so, then
> no issues.
> 
>>  	};
>>  };
>>  
>>

- Péter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-11-20  7:07 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-19 13:26 [PATCH 0/2] arm64: dts: ti: k3-j7200-som/cpb: Correct i2c bus representations Peter Ujfalusi
2020-11-19 13:26 ` [PATCH 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM Peter Ujfalusi
2020-11-19 14:45   ` Vignesh Raghavendra
2020-11-19 13:26 ` [PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 Peter Ujfalusi
2020-11-19 16:10   ` Vignesh Raghavendra
2020-11-20  7:07     ` Peter Ujfalusi

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