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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v4 05/15] memory: tegra: Do not handle spurious interrupts
Date: Mon,  9 Apr 2018 22:28:27 +0300	[thread overview]
Message-ID: <30ec0fb1941e2ea2e10808d59f478f022b06266b.1523301400.git.digetx@gmail.com> (raw)
In-Reply-To: <cover.1523301400.git.digetx@gmail.com>
In-Reply-To: <cover.1523301400.git.digetx@gmail.com>

The ISR reads interrupts-enable mask, but doesn't utilize it. Apply the
mask to the interrupt status and don't handle interrupts that MC driver
haven't asked for. Kernel would disable spurious MC IRQ and report the
error. This would happen only in a case of a very severe bug.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/mc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index a4803ac192bb..d2005b995821 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -252,8 +252,11 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
 	unsigned int bit;
 
 	/* mask all interrupts to avoid flooding */
-	status = mc_readl(mc, MC_INTSTATUS);
 	mask = mc_readl(mc, MC_INTMASK);
+	status = mc_readl(mc, MC_INTSTATUS) & mask;
+
+	if (!status)
+		return IRQ_NONE;
 
 	for_each_set_bit(bit, &status, 32) {
 		const char *error = status_names[bit] ?: "unknown";
-- 
2.16.3

  parent reply	other threads:[~2018-04-09 19:31 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-09 19:28 [PATCH v4 00/15] Memory controller hot reset Dmitry Osipenko
2018-04-09 19:28 ` [PATCH v4 01/15] dt-bindings: arm: tegra: Remove duplicated Tegra30+ MC binding Dmitry Osipenko
2018-04-27  9:35   ` Thierry Reding
2018-04-09 19:28 ` [PATCH v4 02/15] dt-bindings: memory: tegra: Document #reset-cells property of the Tegra30 MC Dmitry Osipenko
2018-04-27  9:35   ` Thierry Reding
2018-04-09 19:28 ` [PATCH v4 03/15] dt-bindings: arm: tegra: Document #reset-cells property of the Tegra20 MC Dmitry Osipenko
2018-04-27  9:35   ` Thierry Reding
2018-04-09 19:28 ` [PATCH v4 04/15] dt-bindings: memory: tegra: Add hot resets definitions Dmitry Osipenko
2018-04-27  9:36   ` Thierry Reding
2018-04-09 19:28 ` Dmitry Osipenko [this message]
2018-04-27  9:36   ` [PATCH v4 05/15] memory: tegra: Do not handle spurious interrupts Thierry Reding
2018-04-09 19:28 ` [PATCH v4 06/15] memory: tegra: Setup interrupts mask before requesting IRQ Dmitry Osipenko
2018-04-27  9:36   ` Thierry Reding
2018-04-09 19:28 ` [PATCH v4 07/15] memory: tegra: Apply interrupts mask per SoC Dmitry Osipenko
2018-04-27  9:36   ` Thierry Reding
2018-04-09 19:28 ` [PATCH v4 08/15] memory: tegra: Remove unused headers inclusions Dmitry Osipenko
2018-04-27  9:37   ` Thierry Reding
2018-04-09 19:28 ` [PATCH v4 09/15] memory: tegra: Squash tegra20-mc into common tegra-mc driver Dmitry Osipenko
2018-04-27  9:34   ` Thierry Reding
2018-04-27 10:13     ` Dmitry Osipenko
2018-04-27 10:24       ` Thierry Reding
2018-04-27 10:56         ` Dmitry Osipenko
2018-04-30  8:07   ` Thierry Reding
2018-04-13 11:33 ` [PATCH v4 10/15] memory: tegra: Introduce memory client hot reset Dmitry Osipenko
2018-04-30  8:08   ` Thierry Reding
2018-04-13 11:33 ` [PATCH v4 11/15] memory: tegra: Add Tegra210 memory controller hot resets Dmitry Osipenko
2018-04-27  9:39   ` Thierry Reding
2018-04-28  8:18     ` Dmitry Osipenko
2018-04-30  8:08       ` Thierry Reding
2018-04-13 11:33 ` [PATCH v4 12/15] memory: tegra: Add Tegra124 " Dmitry Osipenko
2018-04-30  8:08   ` Thierry Reding
2018-04-13 11:33 ` [PATCH v4 13/15] memory: tegra: Add Tegra114 " Dmitry Osipenko
2018-04-30  8:09   ` Thierry Reding
2018-04-13 11:33 ` [PATCH v4 14/15] memory: tegra: Add Tegra30 " Dmitry Osipenko
2018-04-30  8:09   ` Thierry Reding
2018-04-13 11:33 ` [PATCH v4 15/15] memory: tegra: Add Tegra20 " Dmitry Osipenko
2018-04-30  8:09   ` Thierry Reding

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