From: "Andreas Färber" <afaerber@suse.de>
To: Chester Lin <clin@suse.com>, Dong Aisheng <aisheng.dong@nxp.com>,
Fabio Estevam <festevam@gmail.com>,
Shawn Guo <shawnguo@kernel.org>, Jacky Bai <ping.bai@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: s32@nxp.com, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Linus Walleij <linus.walleij@linaro.org>,
Larisa Grigore <larisa.grigore@nxp.com>,
Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>,
Andrei Stefanescu <andrei.stefanescu@nxp.com>,
Radu Pirea <radu-nicolae.pirea@nxp.com>,
Matthias Brugger <mbrugger@suse.com>,
Matthew Nunez <matthew.nunez@nxp.com>,
Phu Luu An <phu.luuan@nxp.com>,
Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Subject: Re: [PATCH v2 2/2] pinctrl: add NXP S32 SoC family support
Date: Tue, 29 Nov 2022 14:40:34 +0100 [thread overview]
Message-ID: <3276c36e-7dfe-ce2d-14d3-20dab732bd76@suse.de> (raw)
In-Reply-To: <20221128054820.1771-3-clin@suse.com>
Hi Chester,
Am 28.11.22 um 06:48 schrieb Chester Lin:
> Add the pinctrl driver for NXP S32 SoC family. This driver is mainly based
> on NXP's downstream implementation on CodeAurora[1].
>
> [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/pinctrl/freescale?h=bsp34.0-5.10.120-rt
>
> Signed-off-by: Matthew Nunez <matthew.nunez@nxp.com>
> Signed-off-by: Phu Luu An <phu.luuan@nxp.com>
> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@nxp.com>
> Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com>
> Signed-off-by: Chester Lin <clin@suse.com>
> ---
>
> Changes in v2:
> - Create a s32_pin_range matrix in the driver for replacing the "nxp,pins"
> property in DT.
> - Refine the compatible name to "nxp,s32g2-siul2-pinctrl".
Thanks.
> - Fix the copyright requested by NXP.
> - Remove a few recipients from the Cc list since these email addresses are no
> longer available.
>
> drivers/pinctrl/freescale/Kconfig | 16 +
> drivers/pinctrl/freescale/Makefile | 2 +
> drivers/pinctrl/freescale/pinctrl-s32.h | 77 ++
> drivers/pinctrl/freescale/pinctrl-s32cc.c | 1003 +++++++++++++++++++++
> drivers/pinctrl/freescale/pinctrl-s32g.c | 773 ++++++++++++++++
> 5 files changed, 1871 insertions(+)
> create mode 100644 drivers/pinctrl/freescale/pinctrl-s32.h
> create mode 100644 drivers/pinctrl/freescale/pinctrl-s32cc.c
> create mode 100644 drivers/pinctrl/freescale/pinctrl-s32g.c
>
> diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
> index 7a32f77792d9..fdd8f5492830 100644
> --- a/drivers/pinctrl/freescale/Kconfig
> +++ b/drivers/pinctrl/freescale/Kconfig
> @@ -217,3 +217,19 @@ config PINCTRL_IMXRT1170
> select PINCTRL_IMX
> help
> Say Y here to enable the imxrt1170 pinctrl driver
> +
> +config PINCTRL_S32CC
> + bool "NXP S32 Common Chassis pinctrl driver core"
> + depends on ARCH_S32 && OF
> + select GENERIC_PINCTRL_GROUPS
> + select GENERIC_PINMUX_FUNCTIONS
> + select GENERIC_PINCONF
> + help
> + Say Y here to enable the NXP S32CC pinctrl driver core
Does this driver core make any sense without a specific driver?
I.e., could this just be a menu-invisible internal option if S32G is the
one the user needs to select anyway?
The alternative would be to leave it and have S32G depend on it,
creating a submenu structure, but that would then still allow to build
the driver core without any users.
> +
> +config PINCTRL_S32G
> + depends on ARCH_S32 && OF
> + bool "NXP S32G pinctrl driver"
> + select PINCTRL_S32CC
> + help
> + Say Y here to enable the pinctrl driver for NXP 32G family SoCs
s/32G/S32G/
> diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
> index 647dff060477..ceb0f61c6215 100644
> --- a/drivers/pinctrl/freescale/Makefile
> +++ b/drivers/pinctrl/freescale/Makefile
> @@ -33,3 +33,5 @@ obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
> obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
> obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
> obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o
> +obj-$(CONFIG_PINCTRL_S32CC) += pinctrl-s32cc.o
> +obj-$(CONFIG_PINCTRL_S32G) += pinctrl-s32g.o
[snip]
Regards,
Andreas
--
SUSE Software Solutions Germany GmbH
Frankenstraße 146, 90461 Nürnberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nürnberg)
next prev parent reply other threads:[~2022-11-29 13:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 5:48 [PATCH v2 0/2] Add pinctrl support for S32 SoC family Chester Lin
2022-11-28 5:48 ` [PATCH v2 1/2] dt-bindings: pinctrl: add schema for NXP S32 SoCs Chester Lin
2022-11-29 14:00 ` Andreas Färber
2022-11-29 14:52 ` Chester Lin
2022-11-30 14:58 ` Krzysztof Kozlowski
2022-12-05 6:16 ` Chester Lin
2022-12-05 9:02 ` Krzysztof Kozlowski
2022-12-05 11:05 ` Chester Lin
2022-12-05 13:26 ` Krzysztof Kozlowski
2022-11-28 5:48 ` [PATCH v2 2/2] pinctrl: add NXP S32 SoC family support Chester Lin
2022-11-29 13:40 ` Andreas Färber [this message]
2022-12-05 7:06 ` Chester Lin
2022-12-07 22:52 ` Linus Walleij
2022-12-07 23:04 ` Fabio Estevam
2022-12-08 21:37 ` Linus Walleij
2022-12-09 4:38 ` Chester Lin
2022-12-09 11:27 ` Linus Walleij
2022-12-14 23:08 ` Saravana Kannan
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