From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22EC6C4320E for ; Wed, 28 Jul 2021 14:09:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08D5D60F45 for ; Wed, 28 Jul 2021 14:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236659AbhG1OJE (ORCPT ); Wed, 28 Jul 2021 10:09:04 -0400 Received: from gloria.sntech.de ([185.11.138.130]:50184 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235464AbhG1OJD (ORCPT ); Wed, 28 Jul 2021 10:09:03 -0400 Received: from [95.90.166.74] (helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m8kEz-0005xo-Uz; Wed, 28 Jul 2021 16:08:57 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Peter Geis Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: Re: [PATCH 7/9] arm64: dts: rockchip: adjust rk3568 pll clocks Date: Wed, 28 Jul 2021 16:08:57 +0200 Message-ID: <3555961.44csPzL39Z@diego> In-Reply-To: <20210728135534.703028-8-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> <20210728135534.703028-8-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, Am Mittwoch, 28. Juli 2021, 15:55:32 CEST schrieb Peter Geis: > The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. > These are set incorrectly by the bootloader, so fix them here. Can you specify where the "should run at" comes from? Normally I'd assume setting desired PLL frequencies would be quite board-specific. So if we're setting defaults for all boards, I'd like some reasoning behind that ;-) ... especially when the other option would be to fix the bootloader. Thanks Heiko > > Signed-off-by: Peter Geis > --- > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 8ba0516eedd8..91ae3c541c1a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -230,6 +230,8 @@ cru: clock-controller@fdd20000 { > rockchip,grf = <&grf>; > #clock-cells = <1>; > #reset-cells = <1>; > + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; > + assigned-clock-rates = <1200000000>, <200000000>; > }; > > i2c0: i2c@fdd40000 { >