[PATCH 0/6] Add IMX8M Mini PCI support

[PATCH 0/6] Add IMX8M Mini PCI support

[Tim Harvey]

The IMX8M Mini PCI controller shares much in common with the existing
SoC's supported by the pci-imx6 driver.

This series adds support for it. Driver changes came from the NXP
downstream vendor kernel [1]

This series depends on Lucas Stach's i.MX8MM GPC improvements and
BLK_CTRL driver and is based on top of his v2 submission [2]

The final patch adds PCIe support to the
Tim
[1] https://source.codeaurora.org/external/imx/linux-imx/
[2]
https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=519251

Tim Harvey (6):
  dt-bindings: imx6q-pcie: add compatible for IMX8MM support
  dt-bindings: reset: imx8mq: add pcie reset
  PCI: imx6: add IMX8MM support
  reset: imx7: add resets for PCIe
  arm64: dts: imx8mm: add PCIe support
  arm64: dts: imx8mm: add gpc iomux compatible

 .../bindings/pci/fsl,imx6q-pcie.txt           |   4 +-
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  38 ++++++-
 drivers/pci/controller/dwc/pci-imx6.c         | 103 +++++++++++++++++-
 drivers/reset/reset-imx7.c                    |   3 +
 include/dt-bindings/reset/imx8mq-reset.h      |   3 +-
 5 files changed, 147 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH 1/6] dt-bindings: imx6q-pcie: add compatible for IMX8MM support

[Tim Harvey]

This adds the DT binding for IMX8MM support to the existing imx6q-pcie
driver which shares most functionality with the IMX8MM.

Additionally a 'fsl,ext-osc' property is defined to note use of an
external oscillator as ref clock vs the internal PLL.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index d8971ab99274..9886e1344fd3 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -10,6 +10,7 @@ Required properties:
 	- "fsl,imx6qp-pcie"
 	- "fsl,imx7d-pcie"
 	- "fsl,imx8mq-pcie"
+	- "fsl,imx8mm-pcie"
 - reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
@@ -19,6 +20,7 @@ Required properties:
 	- "pcie_phy"
 
 Optional properties:
+- fsl,ext-osc: use the external oscillator as ref clock (vs internal PLL)
 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
 - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
@@ -49,7 +51,7 @@ Additional required properties for imx6sx-pcie:
   PCIE_PHY power domains
 - power-domain-names: Must be "pcie", "pcie_phy"
 
-Additional required properties for imx7d-pcie and imx8mq-pcie:
+Additional required properties for imx7d-pcie, imx8mq-pcie, imx8mm-pcie:
 - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
 - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
   IP block
-- 
2.17.1

[PATCH 2/6] dt-bindings: reset: imx8mq: add pcie reset

[Tim Harvey]

Add the reset used by the pcie driver

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 include/dt-bindings/reset/imx8mq-reset.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
index 705870693ec2..20a25ee4a271 100644
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -61,7 +61,8 @@
 #define IMX8MQ_RESET_SW_M4C_RST			50
 #define IMX8MQ_RESET_SW_M4P_RST			51
 #define IMX8MQ_RESET_M4_ENABLE			52
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ	53
 
-#define IMX8MQ_RESET_NUM			53
+#define IMX8MQ_RESET_NUM			54
 
 #endif
-- 
2.17.1

[PATCH 3/6] PCI: imx6: add IMX8MM support

[Tim Harvey]

Add IMX8MM support to the existing driver which shares most
functionality with the IMX8MM.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 80fc98acf097..8fb36d33a244 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -49,6 +49,7 @@ enum imx6_pcie_variants {
 	IMX6QP,
 	IMX7D,
 	IMX8MQ,
+	IMX8MM,
 };
 
 #define IMX6_PCIE_FLAG_IMX6_PHY			BIT(0)
@@ -83,6 +84,7 @@ struct imx6_pcie {
 	struct regulator	*vpcie;
 	struct regulator	*vph;
 	void __iomem		*phy_base;
+	bool			ext_osc;
 
 	/* power domain for pcie */
 	struct device		*pd_pcie;
@@ -139,10 +141,29 @@ struct imx6_pcie {
 #define PCIE_PHY_CMN_REG26		0x98
 #define PCIE_PHY_CMN_REG26_ATT_MODE	0xBC
 
+#define PCIE_PHY_CMN_REG62                      0x188
+#define PCIE_PHY_CMN_REG62_PLL_CLK_OUT          0x08
+#define PCIE_PHY_CMN_REG64                      0x190
+#define PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM       0x8C
+#define PCIE_PHY_CMN_REG75                      0x1D4
+#define PCIE_PHY_CMN_REG75_PLL_DONE             0x3
+#define PCIE_PHY_TRSV_REG5                      0x414
+#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP           0x2D
+#define PCIE_PHY_TRSV_REG6                      0x418
+#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP           0xF
+
 #define PHY_RX_OVRD_IN_LO 0x1005
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN		BIT(5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN		BIT(3)
 
+#define IMX8MM_GPR_PCIE_REF_CLK_SEL		(0x3 << 24)
+#define IMX8MM_GPR_PCIE_REF_CLK_PLL		(0x3 << 24)
+#define IMX8MM_GPR_PCIE_REF_CLK_EXT		(0x2 << 24)
+#define IMX8MM_GPR_PCIE_AUX_EN			BIT(19)
+#define IMX8MM_GPR_PCIE_CMN_RST			BIT(18)
+#define IMX8MM_GPR_PCIE_POWER_OFF		BIT(17)
+#define IMX8MM_GPR_PCIE_SSC_EN			BIT(16)
+
 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
 {
 	struct dw_pcie *pci = imx6_pcie->pci;
@@ -371,6 +392,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX7D:
 	case IMX8MQ:
+	case IMX8MM:
 		reset_control_assert(imx6_pcie->pciephy_reset);
 		reset_control_assert(imx6_pcie->apps_reset);
 		break;
@@ -407,7 +429,6 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 
 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 {
-	WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
 	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 }
 
@@ -447,6 +468,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 	case IMX7D:
 		break;
 	case IMX8MQ:
+	case IMX8MM:
 		ret = clk_prepare_enable(imx6_pcie->pcie_aux);
 		if (ret) {
 			dev_err(dev, "unable to enable pcie_aux clock\n");
@@ -536,6 +558,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX8MQ:
+	case IMX8MM:
 		reset_control_deassert(imx6_pcie->pciephy_reset);
 		break;
 	case IMX7D:
@@ -613,7 +636,74 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 
 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
+	unsigned int offset;
+
 	switch (imx6_pcie->drvdata->variant) {
+	case IMX8MM:
+		offset = imx6_pcie_grp_offset(imx6_pcie);
+
+		dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n",
+				imx6_pcie->ext_osc ? "EXT" : "PLL");
+		if (imx6_pcie->ext_osc) {
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_AUX_EN,
+					IMX8MM_GPR_PCIE_AUX_EN);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_POWER_OFF, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_SSC_EN, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_EXT);
+			udelay(100);
+			/* Do the PHY common block reset */
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_CMN_RST,
+					IMX8MM_GPR_PCIE_CMN_RST);
+			udelay(200);
+		} else {
+			/* Configure the internal PLL as REF clock */
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_AUX_EN,
+					IMX8MM_GPR_PCIE_AUX_EN);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_POWER_OFF, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_SSC_EN, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_PLL);
+			udelay(100);
+			/* Configure the PHY */
+			writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT,
+					imx6_pcie->phy_base + PCIE_PHY_CMN_REG62);
+			writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM,
+					imx6_pcie->phy_base + PCIE_PHY_CMN_REG64);
+			/* Do the PHY common block reset */
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_CMN_RST,
+					IMX8MM_GPR_PCIE_CMN_RST);
+			udelay(200);
+		}
+		/*
+		 * In order to pass the compliance tests.
+		 * Configure the TRSV regiser of iMX8MM PCIe PHY.
+		 */
+		writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP,
+				imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5);
+		writel(PCIE_PHY_TRSV_REG6_GEN2_DEEMP,
+				imx6_pcie->phy_base + PCIE_PHY_TRSV_REG6);
+		break;
 	case IMX8MQ:
 		/*
 		 * TODO: Currently this code assumes external
@@ -753,6 +843,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
 		break;
 	case IMX7D:
 	case IMX8MQ:
+	case IMX8MM:
 		reset_control_deassert(imx6_pcie->apps_reset);
 		break;
 	}
@@ -871,6 +962,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
 				   IMX6Q_GPR12_PCIE_CTL_2, 0);
 		break;
 	case IMX7D:
+	case IMX8MM:
 		reset_control_assert(imx6_pcie->apps_reset);
 		break;
 	default:
@@ -929,6 +1021,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
 				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
 				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
 		break;
+	case IMX8MM:
 	case IMX8MQ:
 		clk_disable_unprepare(imx6_pcie->pcie_aux);
 		break;
@@ -1024,6 +1117,9 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 	if (IS_ERR(pci->dbi_base))
 		return PTR_ERR(pci->dbi_base);
 
+	/* check for EXT osc */
+	imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc");
+
 	/* Fetch GPIOs */
 	imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
 	imx6_pcie->gpio_active_high = of_property_read_bool(node,
@@ -1067,6 +1163,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 					     "pcie_inbound_axi clock missing or invalid\n");
 		break;
 	case IMX8MQ:
+	case IMX8MM:
 		imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
 		if (IS_ERR(imx6_pcie->pcie_aux))
 			return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1202,6 +1299,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 	[IMX8MQ] = {
 		.variant = IMX8MQ,
 	},
+	[IMX8MM] = {
+		.variant = IMX8MM,
+	},
 };
 
 static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1210,6 +1310,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
 	{ .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
 	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
+	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
 	{},
 };
 
-- 
2.17.1

[PATCH 4/6] reset: imx7: add resets for PCIe

[Tim Harvey]

Add reset for PCIe clock and PHY.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/reset/reset-imx7.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..423707e1fd59 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -191,6 +191,7 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
 	[IMX8MQ_RESET_PCIEPHY]			= { SRC_PCIEPHY_RCR,
 						    BIT(2) | BIT(1) },
 	[IMX8MQ_RESET_PCIEPHY_PERST]		= { SRC_PCIEPHY_RCR, BIT(3) },
+	[IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ]	= { SRC_PCIEPHY_RCR, BIT(4) },
 	[IMX8MQ_RESET_PCIE_CTRL_APPS_EN]	= { SRC_PCIEPHY_RCR, BIT(6) },
 	[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF]	= { SRC_PCIEPHY_RCR, BIT(11) },
 	[IMX8MQ_RESET_HDMI_PHY_APB_RESET]	= { SRC_HDMI_RCR, BIT(0) },
@@ -234,7 +235,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
 			udelay(10);
 		break;
 
+	case IMX8MQ_RESET_PCIEPHY_PERST:
 	case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
+	case IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ:
 	case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
 	case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
 	case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
-- 
2.17.1

[PATCH 5/6] arm64: dts: imx8mm: add PCIe support

[Tim Harvey]

Add PCIe node for PCIe support.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 +++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 3bec6b8d52a0..45017f50a11b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1134,6 +1134,10 @@
 				reg = <0x32e50200 0x200>;
 			};
 
+			pcie_phy: pcie-phy@32f00000 {
+				  compatible = "fsl,imx7d-pcie-phy";
+				  reg = <0x32f00000 0x10000>;
+			};
 		};
 
 		dma_apbh: dma-controller@33000000 {
@@ -1233,5 +1237,37 @@
 			reg = <0x3d800000 0x400000>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		pcie0: pcie@33800000 {
+			compatible = "fsl,imx8mm-pcie";
+			reg = <0x33800000 0x400000>,
+			      <0x1ff00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+				 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "clkreq", "turnoff";
+			fsl,imx7d-pcie-phy = <&pcie_phy>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.17.1

[PATCH 6/6] arm64: dts: imx8mm: add gpc iomux compatible

[Tim Harvey]

Add gpc iomux compatible needed for IMX8MM PCIe.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 45017f50a11b..a2de42dc5f61 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -519,7 +519,7 @@
 			};
 
 			gpr: iomuxc-gpr@30340000 {
-				compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+				compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
 				reg = <0x30340000 0x10000>;
 			};
 
-- 
2.17.1

Re: [PATCH 5/6] arm64: dts: imx8mm: add PCIe support

[Rob Herring]

On Fri, Jul 23, 2021 at 2:50 PM Tim Harvey <tharvey@gateworks.com> wrote:
>
> Add PCIe node for PCIe support.
>
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 +++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 3bec6b8d52a0..45017f50a11b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1134,6 +1134,10 @@
>                                 reg = <0x32e50200 0x200>;
>                         };
>
> +                       pcie_phy: pcie-phy@32f00000 {
> +                                 compatible = "fsl,imx7d-pcie-phy";
> +                                 reg = <0x32f00000 0x10000>;

The phy really has 64KB worth of registers? This wastes virtual space
too, but I guess that's 'free' on 64-bit.

> +                       };
>                 };
>
>                 dma_apbh: dma-controller@33000000 {
> @@ -1233,5 +1237,37 @@
>                         reg = <0x3d800000 0x400000>;
>                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>                 };
> +
> +               pcie0: pcie@33800000 {
> +                       compatible = "fsl,imx8mm-pcie";
> +                       reg = <0x33800000 0x400000>,
> +                             <0x1ff00000 0x80000>;
> +                       reg-names = "dbi", "config";

I don't think the DBI space ever has 4MB of registers. And IIRC, only
4KB is used for config space unless ECAM is used.

> +                       #address-cells = <3>;
> +                       #size-cells = <2>;
> +                       device_type = "pci";
> +                       bus-range = <0x00 0xff>;
> +                       ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
> +                                0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
> +                       num-lanes = <1>;
> +                       num-viewport = <4>;

This is deprecated and ignored. The driver has gotten smarter and detects this.

> +                       interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "msi";
> +                       #interrupt-cells = <1>;
> +                       interrupt-map-mask = <0 0 0 0x7>;
> +                       interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> +                       fsl,max-link-speed = <2>;

There's a standard property for this.

> +                       power-domains = <&pgc_pcie>;
> +                       resets = <&src IMX8MQ_RESET_PCIEPHY>,
> +                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
> +                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
> +                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
> +                       reset-names = "pciephy", "apps", "clkreq", "turnoff";

The phy reset belongs in the phy node.

> +                       fsl,imx7d-pcie-phy = <&pcie_phy>;

Didn't we deprecate this? Either way, use the phy binding.

> +                       status = "disabled";
> +               };
>         };
>  };
> --
> 2.17.1
>

Re: [PATCH 0/6] Add IMX8M Mini PCI support

[Ahmad Fatoum]

Hello Tim,

On 23.07.21 22:49, Tim Harvey wrote:
> The IMX8M Mini PCI controller shares much in common with the existing
> SoC's supported by the pci-imx6 driver.
> 
> This series adds support for it. Driver changes came from the NXP
> downstream vendor kernel [1]
> 
> This series depends on Lucas Stach's i.MX8MM GPC improvements and
> BLK_CTRL driver and is based on top of his v2 submission [2]

Are you aware of Lucas' patch series and Rob's remarks there?
https://lore.kernel.org/linux-pci/20210510141509.929120-7-l.stach@pengutronix.de/

Cheers,
Ahmad

> 
> The final patch adds PCIe support to the
> Tim
> [1] https://source.codeaurora.org/external/imx/linux-imx/
> [2]
> https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=519251
> 
> Tim Harvey (6):
>   dt-bindings: imx6q-pcie: add compatible for IMX8MM support
>   dt-bindings: reset: imx8mq: add pcie reset
>   PCI: imx6: add IMX8MM support
>   reset: imx7: add resets for PCIe
>   arm64: dts: imx8mm: add PCIe support
>   arm64: dts: imx8mm: add gpc iomux compatible
> 
>  .../bindings/pci/fsl,imx6q-pcie.txt           |   4 +-
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  38 ++++++-
>  drivers/pci/controller/dwc/pci-imx6.c         | 103 +++++++++++++++++-
>  drivers/reset/reset-imx7.c                    |   3 +
>  include/dt-bindings/reset/imx8mq-reset.h      |   3 +-
>  5 files changed, 147 insertions(+), 4 deletions(-)
> 


-- 
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Re: [PATCH 3/6] PCI: imx6: add IMX8MM support

[Bjorn Helgaas]

Capitalize first letter of subject to match history:

  PCI: imx6: Add IMX8MM support

On Fri, Jul 23, 2021 at 01:49:55PM -0700, Tim Harvey wrote:
> Add IMX8MM support to the existing driver which shares most
> functionality with the IMX8MM.
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++-
>  1 file changed, 102 insertions(+), 1 deletion(-)

> +	case IMX8MM:
> +		offset = imx6_pcie_grp_offset(imx6_pcie);
> +
> +		dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n",
> +				imx6_pcie->ext_osc ? "EXT" : "PLL");
> +		if (imx6_pcie->ext_osc) {
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_REF_CLK_SEL,
> +					IMX8MM_GPR_PCIE_REF_CLK_SEL);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_AUX_EN,
> +					IMX8MM_GPR_PCIE_AUX_EN);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_POWER_OFF, 0);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_SSC_EN, 0);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_REF_CLK_SEL,
> +					IMX8MM_GPR_PCIE_REF_CLK_EXT);
> +			udelay(100);
> +			/* Do the PHY common block reset */
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_CMN_RST,
> +					IMX8MM_GPR_PCIE_CMN_RST);
> +			udelay(200);
> +		} else {
> +			/* Configure the internal PLL as REF clock */
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_REF_CLK_SEL,
> +					IMX8MM_GPR_PCIE_REF_CLK_SEL);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_AUX_EN,
> +					IMX8MM_GPR_PCIE_AUX_EN);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_POWER_OFF, 0);
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_SSC_EN, 0);

Seems like all the above is common to both cases?  If so, it's a shame
to repeat it because it makes it hard to see what's different.

> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_REF_CLK_SEL,
> +					IMX8MM_GPR_PCIE_REF_CLK_PLL);
> +			udelay(100);
> +			/* Configure the PHY */
> +			writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT,
> +					imx6_pcie->phy_base + PCIE_PHY_CMN_REG62);
> +			writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM,
> +					imx6_pcie->phy_base + PCIE_PHY_CMN_REG64);
> +			/* Do the PHY common block reset */
> +			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> +					IMX8MM_GPR_PCIE_CMN_RST,
> +					IMX8MM_GPR_PCIE_CMN_RST);
> +			udelay(200);
> +		}
> +		/*

> +		 * In order to pass the compliance tests.
> +		 * Configure the TRSV regiser of iMX8MM PCIe PHY.

The "In order to ..." line isn't quite a sentence.  Maybe it should be
joined with the second line?

s/regiser/register/ ?

> +		 */
> +		writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP,
> +				imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5);

> +	/* check for EXT osc */

Since you have a comment here, it would be useful to spell out "osc"
for newbies like me.  I assume it's short for "oscillator"?

> +	imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc");

RE: [PATCH 0/6] Add IMX8M Mini PCI support

[Richard Zhu]

Hi Tim:
Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
Some comments in the review cycle.
- One separate PHY driver should be used for i.MX8MM PCIe driver.
- Schema file should be used I think, otherwise the .txt file in the dt-binding.

I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.

Best Regards
Richard Zhu

> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Sent: Thursday, July 29, 2021 10:40 PM
> To: tharvey@gateworks.com; Richard Zhu <hongxing.zhu@nxp.com>; Lucas
> Stach <l.stach@pengutronix.de>; Bjorn Helgaas <bhelgaas@google.com>;
> Rob Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>;
> Sascha Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>;
> dl-linux-imx <linux-imx@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; Krzysztof Wilczyński <kw@linux.com>; Lorenzo
> Pieralisi <lorenzo.pieralisi@arm.com>
> Subject: Re: [PATCH 0/6] Add IMX8M Mini PCI support
> 
> Hello Tim,
> 
> On 23.07.21 22:49, Tim Harvey wrote:
> > The IMX8M Mini PCI controller shares much in common with the existing
> > SoC's supported by the pci-imx6 driver.
> >
> > This series adds support for it. Driver changes came from the NXP
> > downstream vendor kernel [1]
> >
> > This series depends on Lucas Stach's i.MX8MM GPC improvements and
> > BLK_CTRL driver and is based on top of his v2 submission [2]
> 
> Are you aware of Lucas' patch series and Rob's remarks there?
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Flinux-pci%2F20210510141509.929120-7-l.stach%40pengutronix.
> de%2F&amp;data=04%7C01%7Chongxing.zhu%40nxp.com%7C21a3e2ba936
> c443581ea08d9529ebf65%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7
> C0%7C637631664036013517%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sdata=blnp2JkmGAZ2w5JHZHJQoZJSuY1646KAT8cccaI5n%2Fw%3D&amp;
> reserved=0
> 
> Cheers,
> Ahmad
> 
> >
> > The final patch adds PCIe support to the Tim [1]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsour
> >
> ce.codeaurora.org%2Fexternal%2Fimx%2Flinux-imx%2F&amp;data=04%7C0
> 1%7Ch
> >
> ongxing.zhu%40nxp.com%7C21a3e2ba936c443581ea08d9529ebf65%7C686e
> a1d3bc2
> >
> b4c6fa92cd99c5c301635%7C0%7C0%7C637631664036013517%7CUnknown
> %7CTWFpbGZ
> >
> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6M
> n0%3
> >
> D%7C1000&amp;sdata=5IiG4fnzWkcsV2JPnQJ8gAgMhZSuZypTOixD4lV%2BTf
> g%3D&am
> > p;reserved=0
> > [2]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Flist%2F%3Fseries%3D51
> 9
> >
> 251&amp;data=04%7C01%7Chongxing.zhu%40nxp.com%7C21a3e2ba936c44
> 3581ea08
> >
> d9529ebf65%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63763
> 166403601
> >
> 3517%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2lu
> MzIiLCJBT
> >
> iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=M6%2FzPsxRPv%2Fv7a
> ad7uqjDQY
> > 8LhHOX%2B%2FLzxnuW1UrVgE%3D&amp;reserved=0
> >
> > Tim Harvey (6):
> >   dt-bindings: imx6q-pcie: add compatible for IMX8MM support
> >   dt-bindings: reset: imx8mq: add pcie reset
> >   PCI: imx6: add IMX8MM support
> >   reset: imx7: add resets for PCIe
> >   arm64: dts: imx8mm: add PCIe support
> >   arm64: dts: imx8mm: add gpc iomux compatible
> >
> >  .../bindings/pci/fsl,imx6q-pcie.txt           |   4 +-
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  38 ++++++-
> >  drivers/pci/controller/dwc/pci-imx6.c         | 103
> +++++++++++++++++-
> >  drivers/reset/reset-imx7.c                    |   3 +
> >  include/dt-bindings/reset/imx8mq-reset.h      |   3 +-
> >  5 files changed, 147 insertions(+), 4 deletions(-)
> >
> 
> 
> --
> Pengutronix e.K.                           |
> |
> Steuerwalder Str. 21                       |
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.p
> engutronix.de%2F&amp;data=04%7C01%7Chongxing.zhu%40nxp.com%7C21
> a3e2ba936c443581ea08d9529ebf65%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C637631664036013517%7CUnknown%7CTWFpbGZsb3d8ey
> JWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> %7C1000&amp;sdata=jynjjRJZyvooJFXwvz45OU9YB0xr5wA2y%2FkoweEtUq
> U%3D&amp;reserved=0  |
> 31137 Hildesheim, Germany                  | Phone:
> +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:
> +49-5121-206917-5555 |

Re: [PATCH 0/6] Add IMX8M Mini PCI support

[Tim Harvey]

On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <hongxing.zhu@nxp.com> wrote:
>
> Hi Tim:
> Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> Some comments in the review cycle.
> - One separate PHY driver should be used for i.MX8MM PCIe driver.
> - Schema file should be used I think, otherwise the .txt file in the dt-binding.
>
> I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
>
> Best Regards
> Richard Zhu

Richard / Ahmad,

Thanks for your response - I did not see the series from Lucas. I will
drop this and wait for him to complete his work.

Thanks,

Tim

Re: [PATCH 0/6] Add IMX8M Mini PCI support

[Adam Ford]

On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <tharvey@gateworks.com> wrote:
>
> On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <hongxing.zhu@nxp.com> wrote:
> >
> > Hi Tim:
> > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > Some comments in the review cycle.
> > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> >
> > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> >
> > Best Regards
> > Richard Zhu
>
> Richard / Ahmad,
>
> Thanks for your response - I did not see the series from Lucas. I will
> drop this and wait for him to complete his work.
>

Tim,

It appears that the power domain changes have been applied to Shawn's
for-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next

Is there any chance you could rebase and resend this series?

thanks,

adam
> Thanks,
>
> Tim
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 0/6] Add IMX8M Mini PCI support

[Lucas Stach]

Hi Adam,

Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <tharvey@gateworks.com> wrote:
> > 
> > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <hongxing.zhu@nxp.com> wrote:
> > > 
> > > Hi Tim:
> > > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > > Some comments in the review cycle.
> > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> > > 
> > > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> > > 
> > > Best Regards
> > > Richard Zhu
> > 
> > Richard / Ahmad,
> > 
> > Thanks for your response - I did not see the series from Lucas. I will
> > drop this and wait for him to complete his work.
> > 
> 
> Tim,
> 
> It appears that the power domain changes have been applied to Shawn's
> for-next branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
> 
> Is there any chance you could rebase and resend this series?

This wasn't about the power domain series. I also tried to get i.MX8M
PCIe upstream, but the feedback was that we need to split out the PHY
functionality, Richard is currently working on this. There is no point
in resending this series.

Regards,
Lucas

Re: [PATCH 0/6] Add IMX8M Mini PCI support

[Adam Ford]

On Mon, Oct 11, 2021 at 7:30 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Adam,
>
> Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> > On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <tharvey@gateworks.com> wrote:
> > >
> > > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <hongxing.zhu@nxp.com> wrote:
> > > >
> > > > Hi Tim:
> > > > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > > > Some comments in the review cycle.
> > > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> > > >
> > > > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > > > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> > > >
> > > > Best Regards
> > > > Richard Zhu
> > >
> > > Richard / Ahmad,
> > >
> > > Thanks for your response - I did not see the series from Lucas. I will
> > > drop this and wait for him to complete his work.
> > >
> >
> > Tim,
> >
> > It appears that the power domain changes have been applied to Shawn's
> > for-next branch:
> > https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
> >
> > Is there any chance you could rebase and resend this series?
>
> This wasn't about the power domain series. I also tried to get i.MX8M
> PCIe upstream, but the feedback was that we need to split out the PHY
> functionality, Richard is currently working on this. There is no point
> in resending this series.

Sorry.  I missed that part.

adam
>
> Regards,
> Lucas
>

Re: [PATCH 0/6] Add IMX8M Mini PCI support

[Tim Harvey]

On Mon, Oct 11, 2021 at 5:30 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Adam,
>
> Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> > On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <tharvey@gateworks.com> wrote:
> > >
> > > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <hongxing.zhu@nxp.com> wrote:
> > > >
> > > > Hi Tim:
> > > > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > > > Some comments in the review cycle.
> > > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> > > >
> > > > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > > > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> > > >
> > > > Best Regards
> > > > Richard Zhu
> > >
> > > Richard / Ahmad,
> > >
> > > Thanks for your response - I did not see the series from Lucas. I will
> > > drop this and wait for him to complete his work.
> > >
> >
> > Tim,
> >
> > It appears that the power domain changes have been applied to Shawn's
> > for-next branch:
> > https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
> >
> > Is there any chance you could rebase and resend this series?
>
> This wasn't about the power domain series. I also tried to get i.MX8M
> PCIe upstream, but the feedback was that we need to split out the PHY
> functionality, Richard is currently working on this. There is no point
> in resending this series.
>

Lucas,

Thanks for the update.

Richard - please Cc me when you submit as I have several boards to
test IMX8MM PCI with, some with PCI bridges and some without.

Best regards,

Tim

RE: [PATCH 0/6] Add IMX8M Mini PCI support

[Richard Zhu]

> -----Original Message-----
> From: Tim Harvey <tharvey@gateworks.com>
> Sent: Monday, October 11, 2021 11:29 PM
> To: Lucas Stach <l.stach@pengutronix.de>; Richard Zhu
> <hongxing.zhu@nxp.com>
> Cc: Adam Ford <aford173@gmail.com>; Ahmad Fatoum
> <a.fatoum@pengutronix.de>; Bjorn Helgaas <bhelgaas@google.com>; Rob
> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha
> Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>;
> dl-linux-imx <linux-imx@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; Krzysztof Wilczyński <kw@linux.com>; Lorenzo
> Pieralisi <lorenzo.pieralisi@arm.com>
> Subject: Re: [PATCH 0/6] Add IMX8M Mini PCI support
> 
> On Mon, Oct 11, 2021 at 5:30 AM Lucas Stach <l.stach@pengutronix.de>
> wrote:
> >
> > Hi Adam,
> >
> > Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> > > On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <tharvey@gateworks.com>
> wrote:
> > > >
> > > > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <hongxing.zhu@nxp.com>
> wrote:
> > > > >
> > > > > Hi Tim:
> > > > > Just as Ahmad mentioned, Lucas had issue one patch-set to support
> i.MX8MM PCIe.
> > > > > Some comments in the review cycle.
> > > > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > > > - Schema file should be used I think, otherwise the .txt file in the
> dt-binding.
> > > > >
> > > > > I'm preparing one patch-set, but it's relied on the yaml file exchanges
> and power-domain changes(block control and so on).
> > > > > Up to now, I only walking on the first step, trying to exchange the
> dt-binding files to schema yaml file.
> > > > >
> > > > > Best Regards
> > > > > Richard Zhu
> > > >
> > > > Richard / Ahmad,
> > > >
> > > > Thanks for your response - I did not see the series from Lucas. I
> > > > will drop this and wait for him to complete his work.
> > > >
> > >
> > > Tim,
> > >
> > > It appears that the power domain changes have been applied to
> > > Shawn's for-next branch:
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi
> > >
> t.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fshawnguo%2Flinux.
> g
> > >
> it%2Flog%2F%3Fh%3Dfor-next&amp;data=04%7C01%7Chongxing.zhu%40nx
> p.com
> > > %7C1e298d5c31594e5a09df08d98ccbef7a%7C686ea1d3bc2b4c6fa92cd9
> 9c5c3016
> > >
> 35%7C0%7C0%7C637695629794787625%7CUnknown%7CTWFpbGZsb3d8ey
> JWIjoiMC4w
> > >
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sd
> > >
> ata=PY2%2Bvr3s6K5O18lQ9SLY5YCqZHR7Fa%2F2RrbJ%2B041CBU%3D&amp;
> reserve
> > > d=0
> > >
> > > Is there any chance you could rebase and resend this series?
> >
> > This wasn't about the power domain series. I also tried to get i.MX8M
> > PCIe upstream, but the feedback was that we need to split out the PHY
> > functionality, Richard is currently working on this. There is no point
> > in resending this series.
> >
> 
> Lucas,
> 
> Thanks for the update.
> 
> Richard - please Cc me when you submit as I have several boards to test
> IMX8MM PCI with, some with PCI bridges and some without.
[Richard Zhu] Ok, no problem. I would CC you when I issued the v3 patch-set later.
Thanks.

Best Regards
Richard Zhu> 
> Best regards,
> 
> Tim