From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: acme@kernel.org, mingo@redhat.com, linux-kernel@vger.kernel.org,
tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [PATCH 3/9] perf/x86/intel: Support overflows on SLOTS
Date: Tue, 28 May 2019 14:22:32 -0400 [thread overview]
Message-ID: <364b3af4-3bef-b669-a38e-f40dbe5d34c4@linux.intel.com> (raw)
In-Reply-To: <20190528122029.GT2606@hirez.programming.kicks-ass.net>
On 5/28/2019 8:20 AM, Peter Zijlstra wrote:
> On Tue, May 21, 2019 at 02:40:49PM -0700, kan.liang@linux.intel.com wrote:
>> From: Andi Kleen <ak@linux.intel.com>
>>
>> The internal counters used for the metrics can overflow. If this happens
>> an overflow is triggered on the SLOTS fixed counter. Add special code
>> that resets all the slave metric counters in this case.
>
> The SDM also talked about a OVF_PERF_METRICS overflow bit. Which seems
> to suggest something else.
Yes, I think we should handle the bit as well and only update metrics event.
It looks like bit 48 is occupied by INTEL_PMC_IDX_FIXED_BTS.
I will also change
INTEL_PMC_IDX_FIXED_BTS to INTEL_PMC_IDX_FIXED + 15.
INTEL_PMC_IDX_FIXED_METRIC_BASE to INTEL_PMC_IDX_FIXED + 16
Thanks,
Kan
>
>> Signed-off-by: Andi Kleen <ak@linux.intel.com>
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> ---
>> arch/x86/events/intel/core.c | 23 +++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 75ed91a36413..a66dc761f09d 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -2279,12 +2279,35 @@ static void intel_pmu_add_event(struct perf_event *event)
>> intel_pmu_lbr_add(event);
>> }
>>
>> +/* When SLOTS overflowed update all the active topdown-* events */
>> +static void intel_pmu_update_metrics(struct perf_event *event)
>> +{
>> + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>> + int idx;
>> + u64 slots_events;
>> +
>> + slots_events = *(u64 *)cpuc->enabled_events & INTEL_PMC_MSK_ANY_SLOTS;
>> +
>> + for_each_set_bit(idx, (unsigned long *)&slots_events, 64) {
>
> for (idx = INTEL_PMC_IDX_TD_RETIRING;
> idx <= INTEL_PMC_IDX_TD_BE_BOUND; idx++)
>
> perhaps?
>
>> + struct perf_event *ev = cpuc->events[idx];
>> +
>> + if (ev == event)
>> + continue;
>> + x86_perf_event_update(event);
>
> if (ev != event)
> x86_perf_event_update(event)
>> + }
>> +}
>> +
>> /*
>> * Save and restart an expired event. Called by NMI contexts,
>> * so it has to be careful about preempting normal event ops:
>> */
>> int intel_pmu_save_and_restart(struct perf_event *event)
>> {
>> + struct hw_perf_event *hwc = &event->hw;
>> +
>> + if (unlikely(hwc->reg_idx == INTEL_PMC_IDX_FIXED_SLOTS))
>> + intel_pmu_update_metrics(event);
>> +
>> x86_perf_event_update(event);
>> /*
>> * For a checkpointed counter always reset back to 0. This
>> --
>> 2.14.5
>>
next prev parent reply other threads:[~2019-05-28 18:22 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-21 21:40 [PATCH 0/9] TopDown metrics support for Icelake kan.liang
2019-05-21 21:40 ` [PATCH 1/9] perf/core: Support a REMOVE transaction kan.liang
2019-05-21 21:40 ` [PATCH 2/9] perf/x86/intel: Basic support for metrics counters kan.liang
2019-05-28 12:05 ` Peter Zijlstra
2019-05-28 18:20 ` Liang, Kan
2019-05-28 12:15 ` Peter Zijlstra
2019-05-28 18:21 ` Liang, Kan
2019-05-29 7:28 ` Peter Zijlstra
2019-05-29 14:40 ` Liang, Kan
2019-05-29 16:46 ` Peter Zijlstra
2019-05-29 8:14 ` Peter Zijlstra
2019-05-21 21:40 ` [PATCH 3/9] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-05-28 12:20 ` Peter Zijlstra
2019-05-28 18:22 ` Liang, Kan [this message]
2019-05-21 21:40 ` [PATCH 4/9] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-05-28 12:43 ` Peter Zijlstra
2019-05-28 18:23 ` Liang, Kan
2019-05-29 7:30 ` Peter Zijlstra
2019-05-28 12:53 ` Peter Zijlstra
2019-05-28 12:56 ` Peter Zijlstra
2019-05-28 13:32 ` Peter Zijlstra
2019-05-28 13:30 ` Peter Zijlstra
2019-05-28 18:24 ` Liang, Kan
2019-05-29 7:34 ` Peter Zijlstra
2019-05-29 14:41 ` Liang, Kan
2019-05-28 13:43 ` Peter Zijlstra
2019-05-28 18:24 ` Liang, Kan
2019-05-29 7:54 ` Peter Zijlstra
2019-05-29 14:42 ` Liang, Kan
2019-05-29 16:58 ` Peter Zijlstra
2019-06-04 20:39 ` Liang, Kan
2019-05-28 13:48 ` Peter Zijlstra
2019-05-28 18:24 ` Liang, Kan
2019-05-29 7:57 ` Peter Zijlstra
2019-05-29 14:42 ` Liang, Kan
2019-05-21 21:40 ` [PATCH 5/9] perf/x86/intel: Set correct weight for TopDown metrics events kan.liang
2019-05-28 13:50 ` Peter Zijlstra
2019-05-21 21:40 ` [PATCH 6/9] perf/x86/intel: Export new TopDown metrics events for Icelake kan.liang
2019-05-21 21:40 ` [PATCH 7/9] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-05-28 13:52 ` Peter Zijlstra
2019-05-28 18:25 ` Liang, Kan
2019-05-29 7:58 ` Peter Zijlstra
2019-05-21 21:40 ` [PATCH 8/9] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-05-21 21:40 ` [PATCH 9/9] perf, tools: Add documentation for topdown metrics kan.liang
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