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Tue, 28 Jul 2020 14:16:59 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 28 Jul 2020 14:16:59 -0500 Received: from [10.250.100.73] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06SJGvCO018644; Tue, 28 Jul 2020 14:16:57 -0500 Subject: Re: [PATCH 3/4] arm64: dts: ti: Add support for J7200 SoC To: Lokesh Vutla , Tero Kristo , Nishanth Menon , Rob Herring CC: , Linux ARM Mailing List , Sekhar Nori , Kishon Vijay Abraham I , Suman Anna References: <20200723084628.19241-1-lokeshvutla@ti.com> <20200723084628.19241-4-lokeshvutla@ti.com> From: Grygorii Strashko Message-ID: <36788bae-ddcd-a880-ea34-a4919945009c@ti.com> Date: Tue, 28 Jul 2020 22:16:56 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200723084628.19241-4-lokeshvutla@ti.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/07/2020 11:46, Lokesh Vutla wrote: > The J7200 SoC is a part of the K3 Multicore SoC architecture platform. > It is targeted for automotive gateway, vehicle compute systems, > Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. > The SoC aims to meet the complex processing needs of modern embedded > products. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, two clusters of lockstep > capable dual Cortex-R5F MCUs and a Centralized Device Management and > Security Controller (DMSC). > * Configurable L3 Cache and IO-coherent architecture with high data > throughput capable distributed DMA architecture under NAVSS. > * Integrated Ethernet switch supporting up to a total of 4 external ports > in addition to legacy Ethernet switch of up to 2 ports. > * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, > 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C > and I2C, eCAP/eQEP, eHRPWM among other peripherals. > * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > > See J7200 Technical Reference Manual (SPRUIU1, June 2020) > for further details: https://www.ti.com/lit/pdf/spruiu1 > > Signed-off-by: Lokesh Vutla > --- > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++ > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++ > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++ > 3 files changed, 448 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > new file mode 100644 > index 000000000000..70c8f7e941fb > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > @@ -0,0 +1,199 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for J7200 SoC Family Main Domain peripherals > + * > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +&cbass_main { > + msmc_ram: sram@70000000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x70000000 0x0 0x100000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x70000000 0x100000>; > + > + atf-sram@0 { > + reg = <0x0 0x20000>; > + }; > + }; > + > + gic500: interrupt-controller@1800000 { > + compatible = "arm,gic-v3"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > + <0x00 0x01900000 0x00 0x100000>; /* GICR */ > + > + /* vcpumntirq: virtual CPU interface maintenance interrupt */ > + interrupts = ; > + > + gic_its: msi-controller@1820000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x00 0x01820000 0x00 0x10000>; > + socionext,synquacer-pre-its = <0x1000000 0x400000>; > + msi-controller; > + #msi-cells = <1>; > + }; > + }; > + > + main_navss: navss@30000000 { > + compatible = "simple-mfd"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; Can we return back ti,sci-dev-id = <199>; here? it's needed for DMA PSI-L pairing. Option: add it as part of dma/net submission. [...] -- Best regards, grygorii