# cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 xtal                                 7        7        0    24000000          0     0  50000         Y
    fe07a000.serial#xtal_div2         1        1        0    12000000          0     0  50000         Y
       fe07a000.serial#xtal2_clk_sel       1        1        0    12000000          0     0  50000         Y
          fe07a000.serial#use_xtal       1        1        0    12000000          0     0  50000         Y
             fe07a000.serial#baud_div       1        1        0      923077          0     0  50000         Y
    fe07a000.serial#xtal_div3         0        0        0     8000000          0     0  50000         Y
       fe07a000.serial#xtal_clk_sel       0        0        0     8000000          0     0  50000         Y

# 
# stty -F /dev/ttyAML0  115200

# stty -F /dev/ttyAML0 
speed 115200 baud; line = 0;
intr = ^C; quit = ^\; erase = ^?; kill = ^U; eof = ^D; eol = <undef>;
eol2 = <undef>; swtch = <undef>; start = ^Q; stop = ^S; susp = ^Z; rprnt = ^R;
werase = ^W; lnext = ^V; flush = ^O; min = 1; time = 0;
-brkint ixoff -imaxbel