From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D9FEC433F5 for ; Wed, 22 Sep 2021 06:56:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50F5960F23 for ; Wed, 22 Sep 2021 06:56:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232989AbhIVG6E (ORCPT ); Wed, 22 Sep 2021 02:58:04 -0400 Received: from foss.arm.com ([217.140.110.172]:43882 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232799AbhIVG57 (ORCPT ); Wed, 22 Sep 2021 02:57:59 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5B8A6113E; Tue, 21 Sep 2021 23:56:29 -0700 (PDT) Received: from [10.163.73.113] (unknown [10.163.73.113]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0421A3F40C; Tue, 21 Sep 2021 23:56:24 -0700 (PDT) Subject: Re: [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-8-suzuki.poulose@arm.com> From: Anshuman Khandual Message-ID: <378f0d4d-138c-3a79-582a-79849175deb5@arm.com> Date: Wed, 22 Sep 2021 12:27:31 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210921134121.2423546-8-suzuki.poulose@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/21/21 7:11 PM, Suzuki K Poulose wrote: > Add the CPU Partnumbers for the new Arm designs. > > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Will Deacon > Acked-by: Catalin Marinas > Signed-off-by: Suzuki K Poulose Reviewed-by: Anshuman Khandual > --- > arch/arm64/include/asm/cputype.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 6231e1f0abe7..19b8441aa8f2 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -73,6 +73,8 @@ > #define ARM_CPU_PART_CORTEX_A76 0xD0B > #define ARM_CPU_PART_NEOVERSE_N1 0xD0C > #define ARM_CPU_PART_CORTEX_A77 0xD0D > +#define ARM_CPU_PART_CORTEX_A710 0xD47 > +#define ARM_CPU_PART_NEOVERSE_N2 0xD49 > > #define APM_CPU_PART_POTENZA 0x000 > > @@ -113,6 +115,8 @@ > #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) > #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) > #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) > +#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) > +#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) > #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) > #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) > #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) >