[PATCH v4 0/5] SDHCI clock handling fixes and cleanups

[PATCH v4 0/5] SDHCI clock handling fixes and cleanups

[Michał Mirosław]

This patch set combines a few of code improvements for SDHCI clock
handling. First three are small fixes to the code, next two make
the clock calculation code simpler.

Michał Mirosław (5):
  mmc: sdhci: fix base clock usage in preset value
  mmc: sdhci: always obey programmable clock config in preset value
  mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
  mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit
  mmc: sdhci: simplify v2/v3+ clock calculation

 drivers/mmc/host/sdhci-of-arasan.c  |  11 +--
 drivers/mmc/host/sdhci-of-dwcmshc.c |   8 +-
 drivers/mmc/host/sdhci.c            | 123 +++++++++++++---------------
 drivers/mmc/host/sdhci.h            |   4 +-
 4 files changed, 67 insertions(+), 79 deletions(-)

-- 
2.30.2

[PATCH v4 1/5] mmc: sdhci: fix base clock usage in preset value

[Michał Mirosław]

Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read
is overwritten for programmable clock preset, but is carried over for
divided clock preset. This can confuse sdhci_enable_clk() if the register
has enable bits set for some reason at time time of clock calculation.
Remove the read.

Quoting Al Cooper:

sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always
return the divider value without the enable set, so this fixes a case
for DDR52 where the enable was not being cleared when the divider
value was changed.

Cc: stable@vger.kernel.org
Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Al Cooper <alcooperx@gmail.com>

---
v4: no changes
v3: updated commit message
v2: removed truncated sentence from commitmsg

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
 drivers/mmc/host/sdhci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index aba6e10b8605..c7438dd13e3e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1857,7 +1857,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 		if (host->preset_enabled) {
 			u16 pre_val;
 
-			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 			pre_val = sdhci_get_preset_value(host);
 			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
 			if (host->clk_mul &&
-- 
2.30.2

[PATCH v4 2/5] mmc: sdhci: always obey programmable clock config in preset value

[Michał Mirosław]

When host controller uses programmable clock presets but doesn't
advertise programmable clock support, we can only guess what frequency
it generates. Let's at least return correct SDHCI_PROG_CLOCK_MODE bit
value in this case.

Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
v4: no changes
v3: added a comment for this case
v2: no changes
---
 drivers/mmc/host/sdhci.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c7438dd13e3e..3ab60e7f936b 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1859,11 +1859,14 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 
 			pre_val = sdhci_get_preset_value(host);
 			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
-			if (host->clk_mul &&
-				(pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
+			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
 				clk = SDHCI_PROG_CLOCK_MODE;
 				real_div = div + 1;
 				clk_mul = host->clk_mul;
+				if (!clk_mul) {
+					/* The clock frequency is unknown. Assume undivided base. */
+					clk_mul = 1;
+				}
 			} else {
 				real_div = max_t(int, 1, div << 1);
 			}
-- 
2.30.2

[PATCH v4 3/5] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

[Michał Mirosław]

Fix returned clock rate for SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN case.
This fixes real_div value that was calculated as 1 (meaning no division)
instead of 2 with the quirk enabled.

Cc: stable@kernel.vger.org
Fixes: d1955c3a9a1d ("mmc: sdhci: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
v4: no changes
v3: updated commit message
v2: no changes
---
 drivers/mmc/host/sdhci.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 3ab60e7f936b..0993f7d0ce8e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1903,9 +1903,12 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 
 		if (!host->clk_mul || switch_base_clk) {
 			/* Version 3.00 divisors must be a multiple of 2. */
-			if (host->max_clk <= clock)
+			if (host->max_clk <= clock) {
 				div = 1;
-			else {
+				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
+					&& host->max_clk <= 25000000)
+					div = 2;
+			} else {
 				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
 				     div += 2) {
 					if ((host->max_clk / div) <= clock)
@@ -1914,9 +1917,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 			}
 			real_div = div;
 			div >>= 1;
-			if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
-				&& !div && host->max_clk <= 25000000)
-				div = 1;
 		}
 	} else {
 		/* Version 2.00 divisors must be a power of 2. */
-- 
2.30.2

[PATCH v4 4/5] mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit

[Michał Mirosław]

Push handling of clock frequency dependence for
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN quirk to the drivers that use it.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
v4: fix build issue reported by kernel test robot
v3: rebased on v5.14-rc2 and reworded commitmsg
v2: reworded commitmsg
---
 drivers/mmc/host/sdhci-of-arasan.c  | 11 ++++-------
 drivers/mmc/host/sdhci-of-dwcmshc.c |  8 +++++---
 drivers/mmc/host/sdhci.c            |  3 +--
 3 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 737e2bfdedc2..f2a6441ab540 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -452,8 +452,7 @@ static const struct sdhci_ops sdhci_arasan_cqe_ops = {
 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
 	.ops = &sdhci_arasan_cqe_ops,
 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
-	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 };
 
 #ifdef CONFIG_PM_SLEEP
@@ -1118,7 +1117,6 @@ static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
 	.ops = &sdhci_arasan_ops,
 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 			SDHCI_QUIRK2_STOP_WITH_TC,
 };
 
@@ -1141,7 +1139,6 @@ static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
 		SDHCI_QUIRK_32BIT_DMA_SIZE |
 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
 		SDHCI_QUIRK2_STOP_WITH_TC |
 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
@@ -1156,7 +1153,6 @@ static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
 		SDHCI_QUIRK_32BIT_DMA_SIZE |
 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 		SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
 		SDHCI_QUIRK2_STOP_WITH_TC |
 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
@@ -1171,7 +1167,6 @@ static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
 		SDHCI_QUIRK_32BIT_DMA_SIZE |
 		SDHCI_QUIRK_32BIT_ADMA_SIZE,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 		SDHCI_QUIRK2_HOST_OFF_CARD_ON |
 		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
 };
@@ -1197,7 +1192,6 @@ static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
 	.ops = &sdhci_arasan_ops,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 			SDHCI_QUIRK2_STOP_WITH_TC,
 };
 
@@ -1502,6 +1496,9 @@ static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
 	bool dma64;
 	int ret;
 
+	if (sdhci_pltfm_clk_get_max_clock(host) <= 25000000)
+		host->quirks2 |= SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN;
+
 	if (!sdhci_arasan->has_cqe)
 		return sdhci_add_host(host);
 
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index bac874ab0b33..b6b7c4068e90 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -283,14 +283,13 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3568_pdata = {
 	.ops = &sdhci_dwcmshc_rk3568_ops,
 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
-	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-		   SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 };
 
 static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
 {
-	int err;
 	struct rk3568_priv *priv = dwc_priv->priv;
+	int err;
 
 	priv->rockchip_clks[0].id = "axi";
 	priv->rockchip_clks[1].id = "block";
@@ -318,6 +317,9 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
 	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
 
+	if (sdhci_pltfm_clk_get_max_clock(host) <= 25000000)
+		host->quirks2 |= SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN;
+
 	return 0;
 }
 
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0993f7d0ce8e..cfa314e659bc 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1905,8 +1905,7 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 			/* Version 3.00 divisors must be a multiple of 2. */
 			if (host->max_clk <= clock) {
 				div = 1;
-				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
-					&& host->max_clk <= 25000000)
+				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
 					div = 2;
 			} else {
 				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
-- 
2.30.2

[PATCH v4 5/5] mmc: sdhci: simplify v2/v3+ clock calculation

[Michał Mirosław]

For base clock setting, SDHCI V2 differs from V3+ only in allowed divisor
values.  Remove the duplicate version of code and reduce indentation
levels.  We can see now, that 'real_div' can't be zero, so the check is
removed.  While at it, replace divisor search loops with divide-and-clamp
to make the code even more readable.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
v4: no changes
v3: squashed div-conversion and deduplication patches to avoid code churn
v2: no changes
---
 drivers/mmc/host/sdhci.c | 124 ++++++++++++++++++---------------------
 drivers/mmc/host/sdhci.h |   4 +-
 2 files changed, 58 insertions(+), 70 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cfa314e659bc..90bda4150083 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1848,88 +1848,76 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host)
 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 		   unsigned int *actual_clock)
 {
-	int div = 0; /* Initialized for compiler warning */
-	int real_div = div, clk_mul = 1;
+	unsigned int div, real_div, clk_mul = 1;
 	u16 clk = 0;
-	bool switch_base_clk = false;
 
-	if (host->version >= SDHCI_SPEC_300) {
-		if (host->preset_enabled) {
-			u16 pre_val;
+	if (clock == 0)
+		return clk;
+
+	if (host->preset_enabled) {
+		/* Only version 3.00+ can have preset_enabled */
+		u16 pre_val;
+
+		pre_val = sdhci_get_preset_value(host);
+		div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
+		if (!(pre_val & SDHCI_PRESET_CLKGEN_SEL))
+			goto base_div_set;
+
+		clk = SDHCI_PROG_CLOCK_MODE;
+		real_div = div + 1;
+		clk_mul = host->clk_mul;
+		if (!clk_mul) {
+			/* The clock frequency is unknown. Assume undivided base. */
+			clk_mul = 1;
+		}
+
+		goto clock_set;
+	}
+
+	/*
+	 * Check if the Host Controller supports Programmable Clock
+	 * Mode.
+	 */
+	if (host->version >= SDHCI_SPEC_300 && host->clk_mul) {
+		div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock);
+		if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) {
+			/*
+			 * Set Programmable Clock Mode in the Clock
+			 * Control register.
+			 */
+			clk = SDHCI_PROG_CLOCK_MODE;
+			clk_mul = host->clk_mul;
+			real_div = div--;
 
-			pre_val = sdhci_get_preset_value(host);
-			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
-			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
-				clk = SDHCI_PROG_CLOCK_MODE;
-				real_div = div + 1;
-				clk_mul = host->clk_mul;
-				if (!clk_mul) {
-					/* The clock frequency is unknown. Assume undivided base. */
-					clk_mul = 1;
-				}
-			} else {
-				real_div = max_t(int, 1, div << 1);
-			}
 			goto clock_set;
 		}
 
 		/*
-		 * Check if the Host Controller supports Programmable Clock
-		 * Mode.
+		 * Divisor is too big for requested clock rate.
+		 * Fall back to the base clock.
 		 */
-		if (host->clk_mul) {
-			for (div = 1; div <= 1024; div++) {
-				if ((host->max_clk * host->clk_mul / div)
-					<= clock)
-					break;
-			}
-			if ((host->max_clk * host->clk_mul / div) <= clock) {
-				/*
-				 * Set Programmable Clock Mode in the Clock
-				 * Control register.
-				 */
-				clk = SDHCI_PROG_CLOCK_MODE;
-				real_div = div;
-				clk_mul = host->clk_mul;
-				div--;
-			} else {
-				/*
-				 * Divisor can be too small to reach clock
-				 * speed requirement. Then use the base clock.
-				 */
-				switch_base_clk = true;
-			}
-		}
+	}
 
-		if (!host->clk_mul || switch_base_clk) {
-			/* Version 3.00 divisors must be a multiple of 2. */
-			if (host->max_clk <= clock) {
-				div = 1;
-				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
-					div = 2;
-			} else {
-				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
-				     div += 2) {
-					if ((host->max_clk / div) <= clock)
-						break;
-				}
-			}
-			real_div = div;
-			div >>= 1;
-		}
+	div = DIV_ROUND_UP(host->max_clk, clock);
+
+	if (div == 1 && (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN))
+		div = 2;
+
+	if (host->version >= SDHCI_SPEC_300) {
+		/* Version 3.00 divisors must be a multiple of 2. */
+		div = min(div, SDHCI_MAX_DIV_SPEC_300);
+		div = DIV_ROUND_UP(div, 2);
 	} else {
 		/* Version 2.00 divisors must be a power of 2. */
-		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
-			if ((host->max_clk / div) <= clock)
-				break;
-		}
-		real_div = div;
-		div >>= 1;
+		div = min(div, SDHCI_MAX_DIV_SPEC_200);
+		div = roundup_pow_of_two(div) / 2;
 	}
 
+base_div_set:
+	real_div = div * 2 + !div;
+
 clock_set:
-	if (real_div)
-		*actual_clock = (host->max_clk * clk_mul) / real_div;
+	*actual_clock = (host->max_clk * clk_mul) / real_div;
 	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 		<< SDHCI_DIVIDER_HI_SHIFT;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 074dc182b184..a3fa70d91410 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -284,8 +284,8 @@
  * End of controller registers.
  */
 
-#define SDHCI_MAX_DIV_SPEC_200	256
-#define SDHCI_MAX_DIV_SPEC_300	2046
+#define SDHCI_MAX_DIV_SPEC_200	256u
+#define SDHCI_MAX_DIV_SPEC_300	2046u
 
 /*
  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
-- 
2.30.2

Re: [PATCH v4 1/5] mmc: sdhci: fix base clock usage in preset value

[Adrian Hunter]

On 25/07/21 12:20 pm, Michał Mirosław wrote:
> Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read
> is overwritten for programmable clock preset, but is carried over for
> divided clock preset. This can confuse sdhci_enable_clk() if the register
> has enable bits set for some reason at time time of clock calculation.

"time time" -> "time"

> Remove the read.
> 
> Quoting Al Cooper:
> 
> sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always
> return the divider value without the enable set, so this fixes a case
> for DDR52 where the enable was not being cleared when the divider
> value was changed.
> 
> Cc: stable@vger.kernel.org
> Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function")
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> Acked-by: Al Cooper <alcooperx@gmail.com>

Apart from above:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> 
> ---
> v4: no changes
> v3: updated commit message
> v2: removed truncated sentence from commitmsg
> 
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> ---
>  drivers/mmc/host/sdhci.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index aba6e10b8605..c7438dd13e3e 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1857,7 +1857,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>  		if (host->preset_enabled) {
>  			u16 pre_val;
>  
> -			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>  			pre_val = sdhci_get_preset_value(host);
>  			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
>  			if (host->clk_mul &&
> 

Re: [PATCH v4 2/5] mmc: sdhci: always obey programmable clock config in preset value

[Adrian Hunter]

On 25/07/21 12:20 pm, Michał Mirosław wrote:
> When host controller uses programmable clock presets but doesn't
> advertise programmable clock support, we can only guess what frequency
> it generates. Let's at least return correct SDHCI_PROG_CLOCK_MODE bit
> value in this case.

If the preset value doesn't make sense, why use it at all?

> 
> Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function")
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> ---
> v4: no changes
> v3: added a comment for this case
> v2: no changes
> ---
>  drivers/mmc/host/sdhci.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index c7438dd13e3e..3ab60e7f936b 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1859,11 +1859,14 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>  
>  			pre_val = sdhci_get_preset_value(host);
>  			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
> -			if (host->clk_mul &&
> -				(pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
> +			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
>  				clk = SDHCI_PROG_CLOCK_MODE;
>  				real_div = div + 1;
>  				clk_mul = host->clk_mul;
> +				if (!clk_mul) {
> +					/* The clock frequency is unknown. Assume undivided base. */
> +					clk_mul = 1;
> +				}
>  			} else {
>  				real_div = max_t(int, 1, div << 1);
>  			}
> 

Re: [PATCH v4 3/5] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

[Adrian Hunter]

On 25/07/21 12:20 pm, Michał Mirosław wrote:
> Fix returned clock rate for SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN case.
> This fixes real_div value that was calculated as 1 (meaning no division)
> instead of 2 with the quirk enabled.
> 
> Cc: stable@kernel.vger.org
> Fixes: d1955c3a9a1d ("mmc: sdhci: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN")
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>

Notwithstanding comment below:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>


> ---
> v4: no changes
> v3: updated commit message
> v2: no changes
> ---
>  drivers/mmc/host/sdhci.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 3ab60e7f936b..0993f7d0ce8e 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1903,9 +1903,12 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>  
>  		if (!host->clk_mul || switch_base_clk) {
>  			/* Version 3.00 divisors must be a multiple of 2. */
> -			if (host->max_clk <= clock)
> +			if (host->max_clk <= clock) {
>  				div = 1;
> -			else {
> +				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> +					&& host->max_clk <= 25000000)

It is preferred to line break after '&&' and line up e.g.

				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) &&
				    host->max_clk <= 25000000)


> +					div = 2;
> +			} else {
>  				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
>  				     div += 2) {
>  					if ((host->max_clk / div) <= clock)
> @@ -1914,9 +1917,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>  			}
>  			real_div = div;
>  			div >>= 1;
> -			if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> -				&& !div && host->max_clk <= 25000000)
> -				div = 1;
>  		}
>  	} else {
>  		/* Version 2.00 divisors must be a power of 2. */
> 

Re: [PATCH v4 4/5] mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit

[Adrian Hunter]

On 25/07/21 12:20 pm, Michał Mirosław wrote:
> Push handling of clock frequency dependence for
> SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN quirk to the drivers that use it.

What is the max_clk dependency for, and why push it down?

> 
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> ---
> v4: fix build issue reported by kernel test robot
> v3: rebased on v5.14-rc2 and reworded commitmsg
> v2: reworded commitmsg
> ---
>  drivers/mmc/host/sdhci-of-arasan.c  | 11 ++++-------
>  drivers/mmc/host/sdhci-of-dwcmshc.c |  8 +++++---
>  drivers/mmc/host/sdhci.c            |  3 +--
>  3 files changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 737e2bfdedc2..f2a6441ab540 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -452,8 +452,7 @@ static const struct sdhci_ops sdhci_arasan_cqe_ops = {
>  static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
>  	.ops = &sdhci_arasan_cqe_ops,
>  	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> -	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
> +	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
>  };
>  
>  #ifdef CONFIG_PM_SLEEP
> @@ -1118,7 +1117,6 @@ static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
>  	.ops = &sdhci_arasan_ops,
>  	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
>  	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
>  			SDHCI_QUIRK2_STOP_WITH_TC,
>  };
>  
> @@ -1141,7 +1139,6 @@ static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
>  		SDHCI_QUIRK_32BIT_DMA_SIZE |
>  		SDHCI_QUIRK_32BIT_ADMA_SIZE,
>  	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
>  		SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
>  		SDHCI_QUIRK2_STOP_WITH_TC |
>  		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> @@ -1156,7 +1153,6 @@ static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
>  		SDHCI_QUIRK_32BIT_DMA_SIZE |
>  		SDHCI_QUIRK_32BIT_ADMA_SIZE,
>  	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
>  		SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
>  		SDHCI_QUIRK2_STOP_WITH_TC |
>  		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> @@ -1171,7 +1167,6 @@ static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
>  		SDHCI_QUIRK_32BIT_DMA_SIZE |
>  		SDHCI_QUIRK_32BIT_ADMA_SIZE,
>  	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -		SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
>  		SDHCI_QUIRK2_HOST_OFF_CARD_ON |
>  		SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
>  };
> @@ -1197,7 +1192,6 @@ static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
>  static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
>  	.ops = &sdhci_arasan_ops,
>  	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
>  			SDHCI_QUIRK2_STOP_WITH_TC,
>  };
>  
> @@ -1502,6 +1496,9 @@ static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
>  	bool dma64;
>  	int ret;
>  
> +	if (sdhci_pltfm_clk_get_max_clock(host) <= 25000000)
> +		host->quirks2 |= SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN;
> +
>  	if (!sdhci_arasan->has_cqe)
>  		return sdhci_add_host(host);
>  
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index bac874ab0b33..b6b7c4068e90 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -283,14 +283,13 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3568_pdata = {
>  	.ops = &sdhci_dwcmshc_rk3568_ops,
>  	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
>  		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
> -	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> -		   SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
> +	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
>  };
>  
>  static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
>  {
> -	int err;
>  	struct rk3568_priv *priv = dwc_priv->priv;
> +	int err;
>  
>  	priv->rockchip_clks[0].id = "axi";
>  	priv->rockchip_clks[1].id = "block";
> @@ -318,6 +317,9 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
>  	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
>  	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
>  
> +	if (sdhci_pltfm_clk_get_max_clock(host) <= 25000000)
> +		host->quirks2 |= SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN;
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 0993f7d0ce8e..cfa314e659bc 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1905,8 +1905,7 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>  			/* Version 3.00 divisors must be a multiple of 2. */
>  			if (host->max_clk <= clock) {
>  				div = 1;
> -				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> -					&& host->max_clk <= 25000000)
> +				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
>  					div = 2;
>  			} else {
>  				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
> 

Re: [PATCH v4 5/5] mmc: sdhci: simplify v2/v3+ clock calculation

[Adrian Hunter]

On 25/07/21 12:20 pm, Michał Mirosław wrote:
> For base clock setting, SDHCI V2 differs from V3+ only in allowed divisor
> values.  Remove the duplicate version of code and reduce indentation
> levels.  We can see now, that 'real_div' can't be zero, so the check is
> removed.  While at it, replace divisor search loops with divide-and-clamp
> to make the code even more readable.

It doesn't seem simpler to me, just different.

Simpler would mean broken into separate logical functions, getting rid of
the gotos, and above all having the changes broken into separate patches
for easy review.

> 
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> ---
> v4: no changes
> v3: squashed div-conversion and deduplication patches to avoid code churn
> v2: no changes
> ---
>  drivers/mmc/host/sdhci.c | 124 ++++++++++++++++++---------------------
>  drivers/mmc/host/sdhci.h |   4 +-
>  2 files changed, 58 insertions(+), 70 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index cfa314e659bc..90bda4150083 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1848,88 +1848,76 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host)
>  u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>  		   unsigned int *actual_clock)
>  {
> -	int div = 0; /* Initialized for compiler warning */
> -	int real_div = div, clk_mul = 1;
> +	unsigned int div, real_div, clk_mul = 1;
>  	u16 clk = 0;
> -	bool switch_base_clk = false;
>  
> -	if (host->version >= SDHCI_SPEC_300) {
> -		if (host->preset_enabled) {
> -			u16 pre_val;
> +	if (clock == 0)
> +		return clk;
> +
> +	if (host->preset_enabled) {
> +		/* Only version 3.00+ can have preset_enabled */
> +		u16 pre_val;
> +
> +		pre_val = sdhci_get_preset_value(host);
> +		div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
> +		if (!(pre_val & SDHCI_PRESET_CLKGEN_SEL))
> +			goto base_div_set;
> +
> +		clk = SDHCI_PROG_CLOCK_MODE;
> +		real_div = div + 1;
> +		clk_mul = host->clk_mul;
> +		if (!clk_mul) {
> +			/* The clock frequency is unknown. Assume undivided base. */
> +			clk_mul = 1;
> +		}
> +
> +		goto clock_set;
> +	}
> +
> +	/*
> +	 * Check if the Host Controller supports Programmable Clock
> +	 * Mode.
> +	 */
> +	if (host->version >= SDHCI_SPEC_300 && host->clk_mul) {
> +		div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock);
> +		if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) {
> +			/*
> +			 * Set Programmable Clock Mode in the Clock
> +			 * Control register.
> +			 */
> +			clk = SDHCI_PROG_CLOCK_MODE;
> +			clk_mul = host->clk_mul;
> +			real_div = div--;
>  
> -			pre_val = sdhci_get_preset_value(host);
> -			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
> -			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
> -				clk = SDHCI_PROG_CLOCK_MODE;
> -				real_div = div + 1;
> -				clk_mul = host->clk_mul;
> -				if (!clk_mul) {
> -					/* The clock frequency is unknown. Assume undivided base. */
> -					clk_mul = 1;
> -				}
> -			} else {
> -				real_div = max_t(int, 1, div << 1);
> -			}
>  			goto clock_set;
>  		}
>  
>  		/*
> -		 * Check if the Host Controller supports Programmable Clock
> -		 * Mode.
> +		 * Divisor is too big for requested clock rate.
> +		 * Fall back to the base clock.
>  		 */
> -		if (host->clk_mul) {
> -			for (div = 1; div <= 1024; div++) {
> -				if ((host->max_clk * host->clk_mul / div)
> -					<= clock)
> -					break;
> -			}
> -			if ((host->max_clk * host->clk_mul / div) <= clock) {
> -				/*
> -				 * Set Programmable Clock Mode in the Clock
> -				 * Control register.
> -				 */
> -				clk = SDHCI_PROG_CLOCK_MODE;
> -				real_div = div;
> -				clk_mul = host->clk_mul;
> -				div--;
> -			} else {
> -				/*
> -				 * Divisor can be too small to reach clock
> -				 * speed requirement. Then use the base clock.
> -				 */
> -				switch_base_clk = true;
> -			}
> -		}
> +	}
>  
> -		if (!host->clk_mul || switch_base_clk) {
> -			/* Version 3.00 divisors must be a multiple of 2. */
> -			if (host->max_clk <= clock) {
> -				div = 1;
> -				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> -					div = 2;
> -			} else {
> -				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
> -				     div += 2) {
> -					if ((host->max_clk / div) <= clock)
> -						break;
> -				}
> -			}
> -			real_div = div;
> -			div >>= 1;
> -		}
> +	div = DIV_ROUND_UP(host->max_clk, clock);
> +
> +	if (div == 1 && (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN))
> +		div = 2;
> +
> +	if (host->version >= SDHCI_SPEC_300) {
> +		/* Version 3.00 divisors must be a multiple of 2. */
> +		div = min(div, SDHCI_MAX_DIV_SPEC_300);
> +		div = DIV_ROUND_UP(div, 2);
>  	} else {
>  		/* Version 2.00 divisors must be a power of 2. */
> -		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
> -			if ((host->max_clk / div) <= clock)
> -				break;
> -		}
> -		real_div = div;
> -		div >>= 1;
> +		div = min(div, SDHCI_MAX_DIV_SPEC_200);
> +		div = roundup_pow_of_two(div) / 2;
>  	}
>  
> +base_div_set:
> +	real_div = div * 2 + !div;
> +
>  clock_set:
> -	if (real_div)
> -		*actual_clock = (host->max_clk * clk_mul) / real_div;
> +	*actual_clock = (host->max_clk * clk_mul) / real_div;
>  	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
>  	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
>  		<< SDHCI_DIVIDER_HI_SHIFT;
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 074dc182b184..a3fa70d91410 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -284,8 +284,8 @@
>   * End of controller registers.
>   */
>  
> -#define SDHCI_MAX_DIV_SPEC_200	256
> -#define SDHCI_MAX_DIV_SPEC_300	2046
> +#define SDHCI_MAX_DIV_SPEC_200	256u
> +#define SDHCI_MAX_DIV_SPEC_300	2046u
>  
>  /*
>   * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
> 

Re: [PATCH v4 2/5] mmc: sdhci: always obey programmable clock config in preset value

[Michał Mirosław]

On Wed, Aug 04, 2021 at 01:52:21PM +0300, Adrian Hunter wrote:
> On 25/07/21 12:20 pm, Michał Mirosław wrote:
> > When host controller uses programmable clock presets but doesn't
> > advertise programmable clock support, we can only guess what frequency
> > it generates. Let's at least return correct SDHCI_PROG_CLOCK_MODE bit
> > value in this case.
> If the preset value doesn't make sense, why use it at all?

If I understand the spec correctly, when the preset value is used the
values in Clock Control register are ignored by the module and so the
module can also actually use a different clock source than the ones
available to the driver directly. So either way the driver can't be
sure of the exact frequencu used. This is a cleanup to remove a case
when the code ignores a bit's value based on other unspecified assumptions.

[...]
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1859,11 +1859,14 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
> >  
> >  			pre_val = sdhci_get_preset_value(host);
> >  			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
> > -			if (host->clk_mul &&
> > -				(pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
> > +			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
> >  				clk = SDHCI_PROG_CLOCK_MODE;
> >  				real_div = div + 1;
> >  				clk_mul = host->clk_mul;
> > +				if (!clk_mul) {
> > +					/* The clock frequency is unknown. Assume undivided base. */
> > +					clk_mul = 1;
> > +				}
> >  			} else {
> >  				real_div = max_t(int, 1, div << 1);
> >  			}

Re: [PATCH v4 3/5] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

[Michał Mirosław]

On Wed, Aug 04, 2021 at 02:06:55PM +0300, Adrian Hunter wrote:
> On 25/07/21 12:20 pm, Michał Mirosław wrote:
> > Fix returned clock rate for SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN case.
> > This fixes real_div value that was calculated as 1 (meaning no division)
> > instead of 2 with the quirk enabled.
> > 
> > Cc: stable@kernel.vger.org
> > Fixes: d1955c3a9a1d ("mmc: sdhci: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN")
> > Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> 
> Notwithstanding comment below:
> 
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
[...]
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1903,9 +1903,12 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
> >  
> >  		if (!host->clk_mul || switch_base_clk) {
> >  			/* Version 3.00 divisors must be a multiple of 2. */
> > -			if (host->max_clk <= clock)
> > +			if (host->max_clk <= clock) {
> >  				div = 1;
> > -			else {
> > +				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> > +					&& host->max_clk <= 25000000)
> 
> It is preferred to line break after '&&' and line up e.g.
> 
> 				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) &&
> 				    host->max_clk <= 25000000)

This was just old code moved, but fixed for next version.

> 
> 
> > +					div = 2;
> > +			} else {
> >  				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
> >  				     div += 2) {
> >  					if ((host->max_clk / div) <= clock)
> > @@ -1914,9 +1917,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
> >  			}
> >  			real_div = div;
> >  			div >>= 1;
> > -			if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> > -				&& !div && host->max_clk <= 25000000)
> > -				div = 1;
> >  		}
> >  	} else {
> >  		/* Version 2.00 divisors must be a power of 2. */
> > 
> 

Re: [PATCH v4 4/5] mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit

[Michał Mirosław]

On Wed, Aug 04, 2021 at 03:33:56PM +0300, Adrian Hunter wrote:
> On 25/07/21 12:20 pm, Michał Mirosław wrote:
> > Push handling of clock frequency dependence for
> > SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN quirk to the drivers that use it.
> What is the max_clk dependency for, and why push it down?

I guess this is a workaround for a hardware issue. When I wrote this,
there was only a single user. Now I don't know if the second user got
the limit by accident or just uses the flag not knowing it doesn't work
as the quirk name suggests. IOW this makes it easier to fix in drivers
if the limit is wrong or irrelevant. The dependency doesn't feel like
it belongs to the generic driver anyway.

[...]
> > @@ -318,6 +317,9 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
> >  	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
> >  	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
> >  
> > +	if (sdhci_pltfm_clk_get_max_clock(host) <= 25000000)
> > +		host->quirks2 |= SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN;
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 0993f7d0ce8e..cfa314e659bc 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1905,8 +1905,7 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
> >  			/* Version 3.00 divisors must be a multiple of 2. */
> >  			if (host->max_clk <= clock) {
> >  				div = 1;
> > -				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> > -					&& host->max_clk <= 25000000)
> > +				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> >  					div = 2;
> >  			} else {
> >  				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;

Re: [PATCH v4 5/5] mmc: sdhci: simplify v2/v3+ clock calculation

[Michał Mirosław]

On Wed, Aug 04, 2021 at 03:40:38PM +0300, Adrian Hunter wrote:
> On 25/07/21 12:20 pm, Michał Mirosław wrote:
> > For base clock setting, SDHCI V2 differs from V3+ only in allowed divisor
> > values.  Remove the duplicate version of code and reduce indentation
> > levels.  We can see now, that 'real_div' can't be zero, so the check is
> > removed.  While at it, replace divisor search loops with divide-and-clamp
> > to make the code even more readable.
> 
> It doesn't seem simpler to me, just different.
> 
> Simpler would mean broken into separate logical functions, getting rid of
> the gotos, and above all having the changes broken into separate patches
> for easy review.

I've extracted part of the function. It does look better I think, but it
can be improved. Please take a look.

--->8<---

    mmc: sdhci: rework clock calculation
    
    Rework the code by extracting register value and real clock rate
    calculations to a separate function.  This also removes duplicated
    calculations of real_div and divisor search loops.

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cfa314e659bc..9822903841f1 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1845,97 +1845,79 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host)
 	return preset;
 }
 
-u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
+static u16 sdhci_calc_clk_mode(struct sdhci_host *host, int div, bool prog_mode,
 		   unsigned int *actual_clock)
 {
-	int div = 0; /* Initialized for compiler warning */
-	int real_div = div, clk_mul = 1;
+	unsigned int clk_mul, real_div;
 	u16 clk = 0;
-	bool switch_base_clk = false;
-
-	if (host->version >= SDHCI_SPEC_300) {
-		if (host->preset_enabled) {
-			u16 pre_val;
-
-			pre_val = sdhci_get_preset_value(host);
-			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
-			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
-				clk = SDHCI_PROG_CLOCK_MODE;
-				real_div = div + 1;
-				clk_mul = host->clk_mul;
-				if (!clk_mul) {
-					/* The clock frequency is unknown. Assume undivided base. */
-					clk_mul = 1;
-				}
-			} else {
-				real_div = max_t(int, 1, div << 1);
-			}
-			goto clock_set;
-		}
-
-		/*
-		 * Check if the Host Controller supports Programmable Clock
-		 * Mode.
-		 */
-		if (host->clk_mul) {
-			for (div = 1; div <= 1024; div++) {
-				if ((host->max_clk * host->clk_mul / div)
-					<= clock)
-					break;
-			}
-			if ((host->max_clk * host->clk_mul / div) <= clock) {
-				/*
-				 * Set Programmable Clock Mode in the Clock
-				 * Control register.
-				 */
-				clk = SDHCI_PROG_CLOCK_MODE;
-				real_div = div;
-				clk_mul = host->clk_mul;
-				div--;
-			} else {
-				/*
-				 * Divisor can be too small to reach clock
-				 * speed requirement. Then use the base clock.
-				 */
-				switch_base_clk = true;
-			}
-		}
 
-		if (!host->clk_mul || switch_base_clk) {
-			/* Version 3.00 divisors must be a multiple of 2. */
-			if (host->max_clk <= clock) {
-				div = 1;
-				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
-					div = 2;
-			} else {
-				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
-				     div += 2) {
-					if ((host->max_clk / div) <= clock)
-						break;
-				}
-			}
-			real_div = div;
-			div >>= 1;
-		}
+	if (prog_mode) {
+		clk = SDHCI_PROG_CLOCK_MODE;
+		clk_mul = host->max_clk ?: 1;
+		real_div = div + 1;
 	} else {
-		/* Version 2.00 divisors must be a power of 2. */
-		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
-			if ((host->max_clk / div) <= clock)
-				break;
-		}
-		real_div = div;
-		div >>= 1;
+		clk_mul = 1;
+		real_div = div * 2 + !div;
 	}
 
-clock_set:
-	if (real_div)
-		*actual_clock = (host->max_clk * clk_mul) / real_div;
+	*actual_clock = (host->max_clk * clk_mul) / real_div;
+
 	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 		<< SDHCI_DIVIDER_HI_SHIFT;
 
 	return clk;
 }
+
+u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
+		   unsigned int *actual_clock)
+{
+	unsigned int div;
+
+	if (clock == 0)
+		return 0;
+
+	if (host->preset_enabled) {
+		/* Note: Only version 3.00+ can have preset_enabled. */
+
+		u16 pre_val = sdhci_get_preset_value(host);
+		bool prog_mode = !!(pre_val & SDHCI_PRESET_CLKGEN_SEL);
+		div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
+
+		return sdhci_calc_clk_mode(host, div, prog_mode, actual_clock);
+	}
+
+	if (host->version >= SDHCI_SPEC_300 && host->clk_mul) {
+		/* Programmable Clock Mode is supported. */
+
+		div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock) - 1;
+		if (div <= SDHCI_MAX_DIV_SPEC_300 / 2)
+			return sdhci_calc_clk_mode(host, div, true, actual_clock);
+
+		/*
+		 * Divisor is too big for requested clock rate.
+		 * Fall back to the base clock.
+		 */
+	}
+
+	div = DIV_ROUND_UP(host->max_clk, clock);
+
+	if (div == 1 && (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN))
+		div = 2;
+
+	if (host->version >= SDHCI_SPEC_300) {
+		/* Version 3.00 divisor must be 1 or a multiple of 2. */
+		if (div != 1)
+			div += div & 1;
+		div = min(div, SDHCI_MAX_DIV_SPEC_300);
+	} else {
+		/* Version 2.00 divisor must be a power of 2. */
+		div = roundup_pow_of_two(div);
+		div = min(div, SDHCI_MAX_DIV_SPEC_200);
+	}
+
+	return sdhci_calc_clk_mode(host, div / 2, false, actual_clock);
+}
 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
 
 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 074dc182b184..a3fa70d91410 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -284,8 +284,8 @@
  * End of controller registers.
  */
 
-#define SDHCI_MAX_DIV_SPEC_200	256
-#define SDHCI_MAX_DIV_SPEC_300	2046
+#define SDHCI_MAX_DIV_SPEC_200	256u
+#define SDHCI_MAX_DIV_SPEC_300	2046u
 
 /*
  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.

Re: [PATCH v4 2/5] mmc: sdhci: always obey programmable clock config in preset value

[Adrian Hunter]

On 7/08/21 5:05 pm, Michał Mirosław wrote:
> On Wed, Aug 04, 2021 at 01:52:21PM +0300, Adrian Hunter wrote:
>> On 25/07/21 12:20 pm, Michał Mirosław wrote:
>>> When host controller uses programmable clock presets but doesn't
>>> advertise programmable clock support, we can only guess what frequency
>>> it generates. Let's at least return correct SDHCI_PROG_CLOCK_MODE bit
>>> value in this case.
>> If the preset value doesn't make sense, why use it at all?
> 
> If I understand the spec correctly, when the preset value is used the
> values in Clock Control register are ignored by the module and so the
> module can also actually use a different clock source than the ones
> available to the driver directly.

I don't remember, does it say that in the spec?

>                                   So either way the driver can't be
> sure of the exact frequencu used. This is a cleanup to remove a case
> when the code ignores a bit's value based on other unspecified assumptions.

Is this fixing a real issue?  It seems like switching from one undefined
scenario to another.  Are either of which known to have ever happened?

Perhaps we should leave it as is.

> 
> [...]
>>> --- a/drivers/mmc/host/sdhci.c
>>> +++ b/drivers/mmc/host/sdhci.c
>>> @@ -1859,11 +1859,14 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>>>  
>>>  			pre_val = sdhci_get_preset_value(host);
>>>  			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
>>> -			if (host->clk_mul &&
>>> -				(pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
>>> +			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
>>>  				clk = SDHCI_PROG_CLOCK_MODE;
>>>  				real_div = div + 1;
>>>  				clk_mul = host->clk_mul;
>>> +				if (!clk_mul) {
>>> +					/* The clock frequency is unknown. Assume undivided base. */
>>> +					clk_mul = 1;
>>> +				}
>>>  			} else {
>>>  				real_div = max_t(int, 1, div << 1);
>>>  			}

Re: [PATCH v4 4/5] mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit

[Adrian Hunter]

On 7/08/21 5:12 pm, Michał Mirosław wrote:
> On Wed, Aug 04, 2021 at 03:33:56PM +0300, Adrian Hunter wrote:
>> On 25/07/21 12:20 pm, Michał Mirosław wrote:
>>> Push handling of clock frequency dependence for
>>> SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN quirk to the drivers that use it.
>> What is the max_clk dependency for, and why push it down?
> 
> I guess this is a workaround for a hardware issue. When I wrote this,
> there was only a single user. Now I don't know if the second user got
> the limit by accident or just uses the flag not knowing it doesn't work
> as the quirk name suggests. IOW this makes it easier to fix in drivers
> if the limit is wrong or irrelevant. The dependency doesn't feel like
> it belongs to the generic driver anyway.

Would you mind reaching out to the authors of the relevant patches
and drivers to try to find out the purpose of the max_clk dependency,
before we make any changes?


> 
> [...]
>>> @@ -318,6 +317,9 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
>>>  	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
>>>  	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
>>>  
>>> +	if (sdhci_pltfm_clk_get_max_clock(host) <= 25000000)
>>> +		host->quirks2 |= SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN;
>>> +
>>>  	return 0;
>>>  }
>>>  
>>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>>> index 0993f7d0ce8e..cfa314e659bc 100644
>>> --- a/drivers/mmc/host/sdhci.c
>>> +++ b/drivers/mmc/host/sdhci.c
>>> @@ -1905,8 +1905,7 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>>>  			/* Version 3.00 divisors must be a multiple of 2. */
>>>  			if (host->max_clk <= clock) {
>>>  				div = 1;
>>> -				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
>>> -					&& host->max_clk <= 25000000)
>>> +				if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
>>>  					div = 2;
>>>  			} else {
>>>  				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;