From: "Luck, Tony" <tony.luck@intel.com>
To: Borislav Petkov <bp@suse.de>, Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: "linux-efi@vger.kernel.org" <linux-efi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"ard.biesheuvel@linaro.org" <ard.biesheuvel@linaro.org>,
"x86@kernel.org" <x86@kernel.org>
Subject: RE: [PATCH v2 0/8] Decode IA32/X64 CPER
Date: Thu, 1 Mar 2018 16:38:24 +0000 [thread overview]
Message-ID: <3908561D78D1C84285E8C5FCA982C28F7B388473@ORSMSX110.amr.corp.intel.com> (raw)
In-Reply-To: <20180228084321.GA2969@pd.tnic>
> One much more important thing I forgot about yesterday: how is
> this thing playing into our RAS reporting, x86 decoding chain, etc
> infrastructure?
>
> Is CPER bypassing it completely and the firmware is doing everything
> now? I sure hope not.
Intel gives OEMs lots of options to catch and tweak the error path in
BIOS SMM code. So it is possible that some systems may go into
BIOS which would do platform level analysis and create a CPER to
feed to the OS. Hopefully anyone doing that would clear the machine
check bank and suppress CMCI to avoid double reporting the same
error.
> If not, it needs to tie into our infrastructure and the errors need
> to go into the decoding chain where different things look at them and
> filter them.
Good point.
> Tony, what are your plans here?
Nothing solid yet.
> Perhaps we can finally get MCE decoding on Intel too :-)
It's on a mental list ... I should probably add it to our internal
trackers so that we actually do it sooner rather than in some
distant future.
-Tony
prev parent reply other threads:[~2018-03-01 16:38 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-26 19:38 [PATCH v2 0/8] Decode IA32/X64 CPER Yazen Ghannam
2018-02-26 19:38 ` [PATCH v2 1/8] efi: Fix IA32/X64 Processor Error Record definition Yazen Ghannam
2018-02-27 10:47 ` Borislav Petkov
2018-02-27 15:05 ` Ghannam, Yazen
2018-02-26 19:38 ` [PATCH v2 2/8] efi: Decode IA32/X64 Processor Error Section Yazen Ghannam
2018-02-27 11:22 ` Borislav Petkov
2018-02-27 15:13 ` Ghannam, Yazen
2018-02-27 17:00 ` Borislav Petkov
2018-02-27 17:27 ` Ghannam, Yazen
2018-02-27 17:44 ` Borislav Petkov
2018-02-27 18:06 ` Ghannam, Yazen
2018-02-27 18:34 ` Borislav Petkov
2018-02-26 19:38 ` [PATCH v2 3/8] efi: Decode IA32/X64 Processor Error Info Structure Yazen Ghannam
2018-02-27 14:25 ` Borislav Petkov
2018-02-27 15:25 ` Ghannam, Yazen
2018-02-27 17:04 ` Borislav Petkov
2018-02-27 17:46 ` Ghannam, Yazen
2018-02-27 18:02 ` Borislav Petkov
2018-02-27 18:40 ` Ghannam, Yazen
2018-02-27 19:09 ` Borislav Petkov
2018-02-27 21:32 ` Ghannam, Yazen
2018-02-27 22:10 ` Borislav Petkov
2018-02-26 19:39 ` [PATCH v2 4/8] efi: Decode UEFI-defined IA32/X64 Error Structure GUIDs Yazen Ghannam
2018-02-27 14:30 ` Borislav Petkov
2018-02-27 15:28 ` Ghannam, Yazen
2018-02-27 15:31 ` Ard Biesheuvel
2018-02-26 19:39 ` [PATCH v2 5/8] efi: Decode IA32/X64 Cache, TLB, and Bus Check structures Yazen Ghannam
2018-02-27 15:03 ` Borislav Petkov
2018-02-27 15:33 ` Ghannam, Yazen
2018-02-27 17:06 ` Borislav Petkov
2018-02-26 19:39 ` [PATCH v2 6/8] efi: Decode additional IA32/X64 Bus Check fields Yazen Ghannam
2018-02-26 19:39 ` [PATCH v2 7/8] efi: Decode IA32/X64 MS Check structure Yazen Ghannam
2018-02-26 19:39 ` [PATCH v2 8/8] efi: Decode IA32/X64 Context Info structure Yazen Ghannam
2018-02-28 8:43 ` [PATCH v2 0/8] Decode IA32/X64 CPER Borislav Petkov
2018-02-28 15:12 ` Ghannam, Yazen
2018-02-28 16:35 ` Borislav Petkov
2018-02-28 20:58 ` Ghannam, Yazen
2018-03-01 11:59 ` Borislav Petkov
2018-03-23 0:19 ` Ghannam, Yazen
2018-03-23 15:29 ` Borislav Petkov
2018-03-01 16:38 ` Luck, Tony [this message]
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