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(p200300EA8BF1E200FC07C7321A3665AD.dip0.t-ipconnect.de. [2003:ea:8bf1:e200:fc07:c732:1a36:65ad]) by smtp.googlemail.com with ESMTPSA id x186sm83935785wmg.41.2019.01.25.11.23.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 11:23:36 -0800 (PST) Subject: Re: [PATCH] r8169: Load MAC address from device tree if present To: Andrew Lunn Cc: Thierry Reding , "David S. Miller" , Realtek linux nic maintainers , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190125101814.6262-1-thierry.reding@gmail.com> <20190125145711.GF12962@lunn.ch> <42d32783-c433-b859-6ba4-f2864f034871@gmail.com> <20190125190715.GG22211@lunn.ch> From: Heiner Kallweit Message-ID: <39547002-74f3-66c4-93ce-9adf72841b8e@gmail.com> Date: Fri, 25 Jan 2019 20:23:29 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190125190715.GG22211@lunn.ch> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25.01.2019 20:07, Andrew Lunn wrote: >> Andrew, for my understanding: What do you think is wrong with the >> alignment requirement? It was introduced because we do a 32 bit access >> to the start address of the array and want to avoid an unaligned access. > > Hi Heiner > > Because you are doing pointer aliasing, the compiler will by default > generate bad code, doing unaligned access. Adding the attribute works > around this. But it is just a work around. Since this is very slow > path code, i would just avoid the pointer aliasing, write a bit more C > code as Thierry suggested, and the optimiser will probably figure out > what is going on and produce reasonable code. > > Also, in general, by avoiding pointer aliasing, you allow static code > checkers to work better. They are more likely to discover buffer > overruns, etc. > > Andrew > Thanks, good to know. The following doesn't hurt us here, but things like this have to be considered too. According to chip spec: "The ID registers 0-5 are only permitted to write by 4-byte access. Read access can be byte, word, or double word access." Heiner