From: Philippe CORNU <philippe.cornu@st.com>
To: Archit Taneja <architt@codeaurora.org>,
Brian Norris <briannorris@chromium.org>,
Sean Paul <seanpaul@chromium.org>
Cc: Nickey Yang <nickey.yang@rock-chips.com>,
"mark.yao@rock-chips.com" <mark.yao@rock-chips.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"heiko@sntech.de" <heiko@sntech.de>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"airlied@linux.ie" <airlied@linux.ie>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"linux-rockchip@lists.infradead.org"
<linux-rockchip@lists.infradead.org>,
"hl@rock-chips.com" <hl@rock-chips.com>,
"zyw@rock-chips.comg" <zyw@rock-chips.comg>,
"xbl@rock-chips.com" <xbl@rock-chips.com>,
"Kristian Kristensen" <hoegsberg@gmail.com>
Subject: Re: [PATCH v3 3/6] drm/rockchip/dsi: correct Feedback divider setting
Date: Thu, 26 Oct 2017 09:44:14 +0000 [thread overview]
Message-ID: <39862e7a-b03f-f5d9-54db-ff9aef294a9c@st.com> (raw)
In-Reply-To: <c1f17f1e-6e4f-d44d-348e-43157474f3c9@codeaurora.org>
Hi,
On 10/26/2017 06:13 AM, Archit Taneja wrote:
> Hi,
>
> On 10/26/2017 06:39 AM, Brian Norris wrote:
>> On Wed, Oct 25, 2017 at 03:57:19AM -0400, Sean Paul wrote:
>>> Archit asked a question about moving to
>>> dw-mipi-dsi
>>
>> That question made me think though: this approach seems backwards. It
>> seems like someone did copy/paste/fork, and then we're asking the
>> authors of the original driver to un-fork? It seems like this should
>> happen the other way around -- those trying to support a new incarnation
>> should have looked to try to abstract the original driver for their
>> uses first.
>
> Yes, ST wanted to replicate rockchip's version of the mipi DSI driver and
> put it in their folder. If they did that, their KMS driver would have been
> the third driver to implement a third instance of the DW DSI controller
> driver.
> Hisilicon and Rockchip being the other 2.
>
> It was either that or attempt at a common DSI DW bridge driver. I suggested
> the latter.
>
> The ST guys have abstracted out the PHY pieces, which they knew varied
> between
> rockchip and ST. Ideally, they should have also tried to create a RFC
> patch to
> make the rockchip driver use the bridge too. But they didn't do that, and
> the rockchip or hisilicon people were interested in even looking at it,
> even after I CC'ed them.
>
>>
>> IIUC, that's exactly what Rockchip did for much of their Analogix eDP
>> code -- they reworked the Exynos DP driver to split common Analogix code
>> from any Exynos-specific bits.
>
> I get that. I had hoped either ST or Rockchip guys would have done the
> similar
> thing, but no one volunteered.
>
>>
>> And actually, the current stuff in
>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c is completely unused. It
>> exports some functions, but I see no users of it. Is that intended? Is
>
> The ST kms driver uses it:
>
> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>
I confirm STM32 chipsets use the Synopsys dw dsi bridge driver.
I plan to improve this bridge driver by adding new features (see todos +
dsi read, command mode with bta & gpio...).
For the first commit, I did my best to keep the source code as close as
possible to the Rockchip version, in order to ease the port for Rockchip
guys.
>> somebody already working on refactoring existing Rockchip code to use
>> this?
>
> I don't know. If rockchip isn't interested in doing it, we can check with
> Philippe from ST if he can try creating a RFC that converts the rockchip
> driver to use the dw-mipi-dsi driver.
I am not really interested in doing this port for Rockchip (or Hisilicon
or i.MX...) but happy to help anyone that wants to use the dw-mipi-dsi
bridge driver :)
Many thanks,
Philippe :)
>
> Thanks,
> Archit
>
next prev parent reply other threads:[~2017-10-26 9:45 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-25 3:50 [PATCH v3 1/6] drm/rockchip/dsi: Define and use macros for PHY register addresses Nickey Yang
2017-10-25 3:50 ` [PATCH v3 2/6] drm/rockchip/dsi: correct phy parameter setting Nickey Yang
2017-10-25 7:49 ` Sean Paul
2017-10-25 3:51 ` [PATCH v3 3/6] drm/rockchip/dsi: correct Feedback divider setting Nickey Yang
2017-10-25 7:57 ` Sean Paul
2017-10-26 1:09 ` Brian Norris
2017-10-26 4:13 ` Archit Taneja
2017-10-26 9:44 ` Philippe CORNU [this message]
2017-10-26 21:32 ` Brian Norris
2017-11-28 0:29 ` Brian Norris
2017-11-28 0:34 ` Brian Norris
2017-10-25 3:51 ` [PATCH v3 4/6] drm/rockchip/dsi: add dual mipi channel support Nickey Yang
2017-10-25 8:04 ` Sean Paul
2017-10-26 5:11 ` Archit Taneja
2017-10-25 3:51 ` [PATCH v3 5/6] dt-bindings: add the rockchip,dual-channel for dw-mipi-dsi Nickey Yang
2017-10-26 4:53 ` [PATCH v3 5/6] dt-bindings: add the rockchip, dual-channel " Archit Taneja
2017-11-30 17:32 ` Nickey Yang
2017-12-01 12:59 ` Archit Taneja
2017-12-05 1:19 ` Brian Norris
2017-12-05 5:16 ` Archit Taneja
2017-10-25 3:51 ` [PATCH v3 6/6] arm64: dts: rockchip: add mipi_dsi1 support for rk3399 Nickey Yang
2017-10-25 7:47 ` [PATCH v3 1/6] drm/rockchip/dsi: Define and use macros for PHY register addresses Sean Paul
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