From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756242AbcIOVgO convert rfc822-to-8bit (ORCPT ); Thu, 15 Sep 2016 17:36:14 -0400 Received: from mga04.intel.com ([192.55.52.120]:55319 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752174AbcIOVgF (ORCPT ); Thu, 15 Sep 2016 17:36:05 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,341,1470726000"; d="scan'208";a="9175108" From: "Yu, Fenghua" To: Thomas Gleixner CC: "Anvin, H Peter" , Ingo Molnar , "Luck, Tony" , Peter Zijlstra , Tejun Heo , Borislav Petkov , Stephane Eranian , Marcelo Tosatti , "David Carrillo-Cisneros" , Shaohua Li , "Shankar, Ravi V" , Vikas Shivappa , "Prakhya, Sai Praneeth" , linux-kernel , x86 Subject: RE: [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT Thread-Topic: [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT Thread-Index: AQHSCZ5mlIFO+et6+0eGik/kn4XGs6Bvz/IAgAtOu7A= Date: Thu, 15 Sep 2016 21:36:03 +0000 Message-ID: <3E5A0FA7E9CA944F9D5414FEC6C712205DFFA5CD@ORSMSX106.amr.corp.intel.com> References: <1473328647-33116-1-git-send-email-fenghua.yu@intel.com> <1473328647-33116-11-git-send-email-fenghua.yu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.22.254.138] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Thomas Gleixner [mailto:tglx@linutronix.de] > Sent: Thursday, September 08, 2016 2:54 AM > > On Thu, 8 Sep 2016, Fenghua Yu wrote: > > +extern struct static_key rdt_enable_key; void > > +__intel_rdt_sched_in(void *dummy); > > + > > struct clos_cbm_table { > > unsigned long cbm; > > unsigned int clos_refcnt; > > }; > > > > +/* > > + * intel_rdt_sched_in() - Writes the task's CLOSid to IA32_PQR_MSR > > + * > > + * Following considerations are made so that this has minimal impact > > + * on scheduler hot path: > > + * - This will stay as no-op unless we are running on an Intel SKU > > + * which supports L3 cache allocation. > > + * - When support is present and enabled, does not do any > > + * IA32_PQR_MSR writes until the user starts really using the feature > > + * ie creates a rdtgroup directory and assigns a cache_mask thats > > + * different from the root rdtgroup's cache_mask. > > + * - Caches the per cpu CLOSid values and does the MSR write only > > + * when a task with a different CLOSid is scheduled in. That > > + * means the task belongs to a different rdtgroup. > > + * - Closids are allocated so that different rdtgroup directories > > + * with same cache_mask gets the same CLOSid. This minimizes CLOSids > > + * used and reduces MSR write frequency. > > + */ > > +static inline void intel_rdt_sched_in(void) { > > + /* > > + * Call the schedule in code only when RDT is enabled. > > + */ > > + if (static_key_false(&rdt_enable_key)) > > static_branch_[un]likely() is the proper function to use. How to do this? Should I change the line to + if (static_branch_unlikely(&rdt_enable_key)) ? Thanks. -Fenghua