The main thing here is the PCI cacheline size for, for the PCI MWI 
mini-API (that I added).  We need runtime, not compile-time, CPU 
cacheline size detection due to generic vendor kernels.

As IvanK notes, this is a conservative "just-the-fix" change.  A more 
aggressive change is pending later on, that will move cacheline size 
fixups elsewhere (most likely pci_enable_device, but possibly 
pci_set_master).