From: isaku.yamahata@intel.com
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com,
Paolo Bonzini <pbonzini@redhat.com>,
Jim Mattson <jmattson@google.com>,
erdemaktas@google.com, Connor Kuehl <ckuehl@redhat.com>,
Sean Christopherson <seanjc@google.com>
Subject: [RFC PATCH v5 102/104] KVM: TDX: Add methods to ignore accesses to CPU state
Date: Fri, 4 Mar 2022 11:49:58 -0800 [thread overview]
Message-ID: <3a278829a8617b86b36c32b68a82bc727013ace8.1646422845.git.isaku.yamahata@intel.com> (raw)
In-Reply-To: <cover.1646422845.git.isaku.yamahata@intel.com>
From: Sean Christopherson <sean.j.christopherson@intel.com>
TDX protects TDX guest state from VMM. Implements to access methods for
TDX guest state to ignore them or return zero.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
---
arch/x86/kvm/vmx/main.c | 465 +++++++++++++++++++++++++++++++++----
arch/x86/kvm/vmx/tdx.c | 44 ++++
arch/x86/kvm/vmx/x86_ops.h | 17 ++
3 files changed, 483 insertions(+), 43 deletions(-)
diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c
index de9b4a270f20..0515998f7fa5 100644
--- a/arch/x86/kvm/vmx/main.c
+++ b/arch/x86/kvm/vmx/main.c
@@ -228,6 +228,46 @@ static void vt_enable_smi_window(struct kvm_vcpu *vcpu)
vmx_enable_smi_window(vcpu);
}
+static bool vt_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
+ void *insn, int insn_len)
+{
+ if (is_td_vcpu(vcpu))
+ return false;
+
+ return vmx_can_emulate_instruction(vcpu, emul_type, insn, insn_len);
+}
+
+static int vt_check_intercept(struct kvm_vcpu *vcpu,
+ struct x86_instruction_info *info,
+ enum x86_intercept_stage stage,
+ struct x86_exception *exception)
+{
+ /*
+ * This call back is triggered by the x86 instruction emulator. TDX
+ * doesn't allow guest memory inspection.
+ */
+ if (KVM_BUG_ON(is_td_vcpu(vcpu), vcpu->kvm))
+ return X86EMUL_UNHANDLEABLE;
+
+ return vmx_check_intercept(vcpu, info, stage, exception);
+}
+
+static bool vt_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return true;
+
+ return vmx_apic_init_signal_blocked(vcpu);
+}
+
+static void vt_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return tdx_set_virtual_apic_mode(vcpu);
+
+ return vmx_set_virtual_apic_mode(vcpu);
+}
+
static void vt_apicv_post_state_restore(struct kvm_vcpu *vcpu)
{
if (is_td_vcpu(vcpu))
@@ -236,6 +276,31 @@ static void vt_apicv_post_state_restore(struct kvm_vcpu *vcpu)
return vmx_apicv_post_state_restore(vcpu);
}
+static void vt_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ return vmx_hwapic_irr_update(vcpu, max_irr);
+}
+
+static void vt_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ return vmx_hwapic_isr_update(vcpu, max_isr);
+}
+
+static bool vt_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
+{
+ /* TDX doesn't support L2 at the moment. */
+ if (WARN_ON_ONCE(is_td_vcpu(vcpu)))
+ return false;
+
+ return vmx_guest_apic_has_interrupt(vcpu);
+}
+
static int vt_sync_pir_to_irr(struct kvm_vcpu *vcpu)
{
if (is_td_vcpu(vcpu))
@@ -272,6 +337,179 @@ static void vt_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
kvm_vcpu_deliver_sipi_vector(vcpu, vector);
}
+static void vt_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ return vmx_vcpu_after_set_cpuid(vcpu);
+}
+
+static void vt_update_exception_bitmap(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_update_exception_bitmap(vcpu);
+}
+
+static u64 vt_get_segment_base(struct kvm_vcpu *vcpu, int seg)
+{
+ if (is_td_vcpu(vcpu))
+ return tdx_get_segment_base(vcpu, seg);
+
+ return vmx_get_segment_base(vcpu, seg);
+}
+
+static void vt_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var,
+ int seg)
+{
+ if (is_td_vcpu(vcpu))
+ return tdx_get_segment(vcpu, var, seg);
+
+ vmx_get_segment(vcpu, var, seg);
+}
+
+static void vt_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var,
+ int seg)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_segment(vcpu, var, seg);
+}
+
+static int vt_get_cpl(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return tdx_get_cpl(vcpu);
+
+ return vmx_get_cpl(vcpu);
+}
+
+static void vt_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_get_cs_db_l_bits(vcpu, db, l);
+}
+
+static void vt_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_cr0(vcpu, cr0);
+}
+
+static void vt_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_cr4(vcpu, cr4);
+}
+
+static int vt_set_efer(struct kvm_vcpu *vcpu, u64 efer)
+{
+ if (is_td_vcpu(vcpu))
+ return 0;
+
+ return vmx_set_efer(vcpu, efer);
+}
+
+static void vt_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
+{
+ if (is_td_vcpu(vcpu)) {
+ memset(dt, 0, sizeof(*dt));
+ return;
+ }
+
+ vmx_get_idt(vcpu, dt);
+}
+
+static void vt_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_idt(vcpu, dt);
+}
+
+static void vt_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
+{
+ if (is_td_vcpu(vcpu)) {
+ memset(dt, 0, sizeof(*dt));
+ return;
+ }
+
+ vmx_get_gdt(vcpu, dt);
+}
+
+static void vt_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_gdt(vcpu, dt);
+}
+
+static void vt_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_dr7(vcpu, val);
+}
+
+static void vt_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
+{
+ /*
+ * MOV-DR exiting is always cleared for TD guest, even in debug mode.
+ * Thus KVM_DEBUGREG_WONT_EXIT can never be set and it should never
+ * reach here for TD vcpu.
+ */
+ if (KVM_BUG_ON(is_td_vcpu(vcpu), vcpu->kvm))
+ return;
+
+ vmx_sync_dirty_debug_regs(vcpu);
+}
+
+static void vt_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
+{
+ if (is_td_vcpu(vcpu)) {
+ tdx_cache_reg(vcpu, reg);
+ return;
+ }
+
+ vmx_cache_reg(vcpu, reg);
+}
+
+static unsigned long vt_get_rflags(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return tdx_get_rflags(vcpu);
+
+ return vmx_get_rflags(vcpu);
+}
+
+static void vt_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_set_rflags(vcpu, rflags);
+}
+
+static bool vt_get_if_flag(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return false;
+
+ return vmx_get_if_flag(vcpu);
+}
+
static void vt_flush_tlb_all(struct kvm_vcpu *vcpu)
{
if (is_td_vcpu(vcpu))
@@ -388,6 +626,15 @@ static u32 vt_get_interrupt_shadow(struct kvm_vcpu *vcpu)
return vmx_get_interrupt_shadow(vcpu);
}
+static void vt_patch_hypercall(struct kvm_vcpu *vcpu,
+ unsigned char *hypercall)
+{
+ if (KVM_BUG_ON(is_td_vcpu(vcpu), vcpu->kvm))
+ return;
+
+ vmx_patch_hypercall(vcpu, hypercall);
+}
+
static void vt_inject_irq(struct kvm_vcpu *vcpu)
{
if (is_td_vcpu(vcpu))
@@ -396,6 +643,14 @@ static void vt_inject_irq(struct kvm_vcpu *vcpu)
vmx_inject_irq(vcpu);
}
+static void vt_queue_exception(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_queue_exception(vcpu);
+}
+
static void vt_cancel_injection(struct kvm_vcpu *vcpu)
{
if (is_td_vcpu(vcpu))
@@ -428,6 +683,130 @@ static void vt_request_immediate_exit(struct kvm_vcpu *vcpu)
vmx_request_immediate_exit(vcpu);
}
+static void vt_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_update_cr8_intercept(vcpu, tpr, irr);
+}
+
+static void vt_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
+{
+ if (WARN_ON_ONCE(is_td_vcpu(vcpu)))
+ return;
+
+ vmx_set_apic_access_page_addr(vcpu);
+}
+
+static void vt_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
+{
+ if (WARN_ON_ONCE(is_td_vcpu(vcpu)))
+ return;
+
+ vmx_refresh_apicv_exec_ctrl(vcpu);
+}
+
+static void vt_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_load_eoi_exitmap(vcpu, eoi_exit_bitmap);
+}
+
+static int vt_set_tss_addr(struct kvm *kvm, unsigned int addr)
+{
+ if (is_td(kvm))
+ return 0;
+
+ return vmx_set_tss_addr(kvm, addr);
+}
+
+static int vt_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
+{
+ if (is_td(kvm))
+ return 0;
+
+ return vmx_set_identity_map_addr(kvm, ident_addr);
+}
+
+static u64 vt_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
+{
+ if (is_td_vcpu(vcpu)) {
+ if (is_mmio)
+ return MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
+ return MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT;
+ }
+
+ return vmx_get_mt_mask(vcpu, gfn, is_mmio);
+}
+
+static u64 vt_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
+{
+ /* TDX doesn't support L2 guest at the moment. */
+ if (KVM_BUG_ON(is_td_vcpu(vcpu), vcpu->kvm))
+ return 0;
+
+ return vmx_get_l2_tsc_offset(vcpu);
+}
+
+static u64 vt_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
+{
+ /* TDX doesn't support L2 guest at the moment. */
+ if (KVM_BUG_ON(is_td_vcpu(vcpu), vcpu->kvm))
+ return 0;
+
+ return vmx_get_l2_tsc_multiplier(vcpu);
+}
+
+static void vt_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
+{
+ /* In TDX, tsc offset can't be changed. */
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_write_tsc_offset(vcpu, offset);
+}
+
+static void vt_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
+{
+ /* In TDX, tsc multiplier can't be changed. */
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_write_tsc_multiplier(vcpu, multiplier);
+}
+
+static void vt_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
+{
+ if (is_td_vcpu(vcpu))
+ return;
+
+ vmx_update_cpu_dirty_logging(vcpu);
+}
+
+#ifdef CONFIG_X86_64
+static int vt_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
+ bool *expired)
+{
+ /* VMX-preemption timer isn't available for TDX. */
+ if (is_td_vcpu(vcpu))
+ return -EINVAL;
+
+ return vmx_set_hv_timer(vcpu, guest_deadline_tsc, expired);
+}
+
+static void vt_cancel_hv_timer(struct kvm_vcpu *vcpu)
+{
+ /* VMX-preemption timer can't be set. Set vt_set_hv_timer(). */
+ if (KVM_BUG_ON(is_td_vcpu(vcpu), vcpu->kvm))
+ return;
+
+ vmx_cancel_hv_timer(vcpu);
+}
+#endif
+
static void vt_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
u64 *info1, u64 *info2, u32 *intr_info, u32 *error_code)
{
@@ -480,29 +859,29 @@ struct kvm_x86_ops vt_x86_ops __initdata = {
.vcpu_load = vt_vcpu_load,
.vcpu_put = vt_vcpu_put,
- .update_exception_bitmap = vmx_update_exception_bitmap,
+ .update_exception_bitmap = vt_update_exception_bitmap,
.get_msr_feature = vmx_get_msr_feature,
.get_msr = vt_get_msr,
.set_msr = vt_set_msr,
- .get_segment_base = vmx_get_segment_base,
- .get_segment = vmx_get_segment,
- .set_segment = vmx_set_segment,
- .get_cpl = vmx_get_cpl,
- .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
- .set_cr0 = vmx_set_cr0,
+ .get_segment_base = vt_get_segment_base,
+ .get_segment = vt_get_segment,
+ .set_segment = vt_set_segment,
+ .get_cpl = vt_get_cpl,
+ .get_cs_db_l_bits = vt_get_cs_db_l_bits,
+ .set_cr0 = vt_set_cr0,
.is_valid_cr4 = vmx_is_valid_cr4,
- .set_cr4 = vmx_set_cr4,
- .set_efer = vmx_set_efer,
- .get_idt = vmx_get_idt,
- .set_idt = vmx_set_idt,
- .get_gdt = vmx_get_gdt,
- .set_gdt = vmx_set_gdt,
- .set_dr7 = vmx_set_dr7,
- .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
- .cache_reg = vmx_cache_reg,
- .get_rflags = vmx_get_rflags,
- .set_rflags = vmx_set_rflags,
- .get_if_flag = vmx_get_if_flag,
+ .set_cr4 = vt_set_cr4,
+ .set_efer = vt_set_efer,
+ .get_idt = vt_get_idt,
+ .set_idt = vt_set_idt,
+ .get_gdt = vt_get_gdt,
+ .set_gdt = vt_set_gdt,
+ .set_dr7 = vt_set_dr7,
+ .sync_dirty_debug_regs = vt_sync_dirty_debug_regs,
+ .cache_reg = vt_cache_reg,
+ .get_rflags = vt_get_rflags,
+ .set_rflags = vt_set_rflags,
+ .get_if_flag = vt_get_if_flag,
.tlb_flush_all = vt_flush_tlb_all,
.tlb_flush_current = vt_flush_tlb_current,
@@ -516,10 +895,10 @@ struct kvm_x86_ops vt_x86_ops __initdata = {
.update_emulated_instruction = vmx_update_emulated_instruction,
.set_interrupt_shadow = vt_set_interrupt_shadow,
.get_interrupt_shadow = vt_get_interrupt_shadow,
- .patch_hypercall = vmx_patch_hypercall,
+ .patch_hypercall = vt_patch_hypercall,
.set_irq = vt_inject_irq,
.set_nmi = vt_inject_nmi,
- .queue_exception = vmx_queue_exception,
+ .queue_exception = vt_queue_exception,
.cancel_injection = vt_cancel_injection,
.interrupt_allowed = vt_interrupt_allowed,
.nmi_allowed = vt_nmi_allowed,
@@ -527,39 +906,39 @@ struct kvm_x86_ops vt_x86_ops __initdata = {
.set_nmi_mask = vt_set_nmi_mask,
.enable_nmi_window = vt_enable_nmi_window,
.enable_irq_window = vt_enable_irq_window,
- .update_cr8_intercept = vmx_update_cr8_intercept,
- .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
- .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
- .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
- .load_eoi_exitmap = vmx_load_eoi_exitmap,
+ .update_cr8_intercept = vt_update_cr8_intercept,
+ .set_virtual_apic_mode = vt_set_virtual_apic_mode,
+ .set_apic_access_page_addr = vt_set_apic_access_page_addr,
+ .refresh_apicv_exec_ctrl = vt_refresh_apicv_exec_ctrl,
+ .load_eoi_exitmap = vt_load_eoi_exitmap,
.apicv_post_state_restore = vt_apicv_post_state_restore,
.check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
- .hwapic_irr_update = vmx_hwapic_irr_update,
- .hwapic_isr_update = vmx_hwapic_isr_update,
- .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
+ .hwapic_irr_update = vt_hwapic_irr_update,
+ .hwapic_isr_update = vt_hwapic_isr_update,
+ .guest_apic_has_interrupt = vt_guest_apic_has_interrupt,
.sync_pir_to_irr = vt_sync_pir_to_irr,
.deliver_interrupt = vt_deliver_interrupt,
.dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
.apicv_has_pending_interrupt = vt_apicv_has_pending_interrupt,
- .set_tss_addr = vmx_set_tss_addr,
- .set_identity_map_addr = vmx_set_identity_map_addr,
- .get_mt_mask = vmx_get_mt_mask,
+ .set_tss_addr = vt_set_tss_addr,
+ .set_identity_map_addr = vt_set_identity_map_addr,
+ .get_mt_mask = vt_get_mt_mask,
.get_exit_info = vt_get_exit_info,
- .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
+ .vcpu_after_set_cpuid = vt_vcpu_after_set_cpuid,
.has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
- .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
- .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
- .write_tsc_offset = vmx_write_tsc_offset,
- .write_tsc_multiplier = vmx_write_tsc_multiplier,
+ .get_l2_tsc_offset = vt_get_l2_tsc_offset,
+ .get_l2_tsc_multiplier = vt_get_l2_tsc_multiplier,
+ .write_tsc_offset = vt_write_tsc_offset,
+ .write_tsc_multiplier = vt_write_tsc_multiplier,
.load_mmu_pgd = vt_load_mmu_pgd,
- .check_intercept = vmx_check_intercept,
+ .check_intercept = vt_check_intercept,
.handle_exit_irqoff = vt_handle_exit_irqoff,
.request_immediate_exit = vt_request_immediate_exit,
@@ -567,7 +946,7 @@ struct kvm_x86_ops vt_x86_ops __initdata = {
.sched_in = vt_sched_in,
.cpu_dirty_log_size = PML_ENTITY_NUM,
- .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
+ .update_cpu_dirty_logging = vt_update_cpu_dirty_logging,
.pmu_ops = &intel_pmu_ops,
.nested_ops = &vmx_nested_ops,
@@ -576,8 +955,8 @@ struct kvm_x86_ops vt_x86_ops __initdata = {
.start_assignment = vmx_pi_start_assignment,
#ifdef CONFIG_X86_64
- .set_hv_timer = vmx_set_hv_timer,
- .cancel_hv_timer = vmx_cancel_hv_timer,
+ .set_hv_timer = vt_set_hv_timer,
+ .cancel_hv_timer = vt_cancel_hv_timer,
#endif
.setup_mce = vmx_setup_mce,
@@ -587,8 +966,8 @@ struct kvm_x86_ops vt_x86_ops __initdata = {
.leave_smm = vt_leave_smm,
.enable_smi_window = vt_enable_smi_window,
- .can_emulate_instruction = vmx_can_emulate_instruction,
- .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
+ .can_emulate_instruction = vt_can_emulate_instruction,
+ .apic_init_signal_blocked = vt_apic_init_signal_blocked,
.migrate_timers = vmx_migrate_timers,
.msr_filter_changed = vmx_msr_filter_changed,
diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
index 7bbf6271967b..55a6fd218fc7 100644
--- a/arch/x86/kvm/vmx/tdx.c
+++ b/arch/x86/kvm/vmx/tdx.c
@@ -3,6 +3,7 @@
#include <linux/mmu_context.h>
#include <asm/fpu/xcr.h>
+#include <asm/virtext.h>
#include <asm/tdx.h>
#include "capabilities.h"
@@ -1717,6 +1718,49 @@ void tdx_enable_smi_window(struct kvm_vcpu *vcpu)
vcpu->arch.smi_pending = false;
}
+void tdx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
+{
+ /* Only x2APIC mode is supported for TD. */
+ WARN_ON_ONCE(kvm_get_apic_mode(vcpu) != LAPIC_MODE_X2APIC);
+}
+
+int tdx_get_cpl(struct kvm_vcpu *vcpu)
+{
+ return 0;
+}
+
+void tdx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
+{
+ kvm_register_mark_available(vcpu, reg);
+ switch (reg) {
+ case VCPU_REGS_RSP:
+ case VCPU_REGS_RIP:
+ case VCPU_EXREG_PDPTR:
+ case VCPU_EXREG_CR0:
+ case VCPU_EXREG_CR3:
+ case VCPU_EXREG_CR4:
+ break;
+ default:
+ KVM_BUG_ON(1, vcpu->kvm);
+ break;
+ }
+}
+
+unsigned long tdx_get_rflags(struct kvm_vcpu *vcpu)
+{
+ return 0;
+}
+
+u64 tdx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
+{
+ return 0;
+}
+
+void tdx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
+{
+ memset(var, 0, sizeof(*var));
+}
+
static int tdx_capabilities(struct kvm *kvm, struct kvm_tdx_cmd *cmd)
{
struct kvm_tdx_capabilities __user *user_caps;
diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h
index 19d793609cc4..7cd29b586e43 100644
--- a/arch/x86/kvm/vmx/x86_ops.h
+++ b/arch/x86/kvm/vmx/x86_ops.h
@@ -163,6 +163,14 @@ int tdx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection);
int tdx_enter_smm(struct kvm_vcpu *vcpu, char *smstate);
int tdx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate);
void tdx_enable_smi_window(struct kvm_vcpu *vcpu);
+void tdx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
+
+int tdx_get_cpl(struct kvm_vcpu *vcpu);
+void tdx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg);
+unsigned long tdx_get_rflags(struct kvm_vcpu *vcpu);
+bool tdx_is_emulated_msr(u32 index, bool write);
+u64 tdx_get_segment_base(struct kvm_vcpu *vcpu, int seg);
+void tdx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
int tdx_vm_ioctl(struct kvm *kvm, void __user *argp);
int tdx_vcpu_ioctl(struct kvm_vcpu *vcpu, void __user *argp);
@@ -203,10 +211,19 @@ static inline void tdx_get_exit_info(
static inline bool tdx_is_emulated_msr(u32 index, bool write) { return false; }
static inline int tdx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) { return 1; }
static inline int tdx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) { return 1; }
+
static inline int tdx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) { return false; }
static inline int tdx_enter_smm(struct kvm_vcpu *vcpu, char *smstate) { return 0; }
static inline int tdx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) { return 0; }
static inline void tdx_enable_smi_window(struct kvm_vcpu *vcpu) {}
+static inline void tdx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) {}
+
+static inline int tdx_get_cpl(struct kvm_vcpu *vcpu) { return 0; }
+static inline void tdx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) {}
+static inline unsigned long tdx_get_rflags(struct kvm_vcpu *vcpu) { return 0; }
+static inline u64 tdx_get_segment_base(struct kvm_vcpu *vcpu, int seg) { return 0;}
+static inline void tdx_get_segment(
+ struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) {}
static inline int tdx_vm_ioctl(struct kvm *kvm, void __user *argp) { return -EOPNOTSUPP; }
static inline int tdx_vcpu_ioctl(struct kvm_vcpu *vcpu, void __user *argp) { return -EOPNOTSUPP; }
--
2.25.1
next prev parent reply other threads:[~2022-03-04 19:59 UTC|newest]
Thread overview: 310+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-04 19:48 [RFC PATCH v5 000/104] KVM TDX basic feature support isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 001/104] KVM: VMX: Move out vmx_x86_ops to 'main.c' to wrap VMX and TDX isaku.yamahata
2022-03-13 13:45 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 002/104] x86/virt/tdx: export platform_has_tdx isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 003/104] KVM: TDX: Detect CPU feature on kernel module initialization isaku.yamahata
2022-03-13 13:49 ` Paolo Bonzini
2022-03-14 18:34 ` Isaku Yamahata
2022-04-08 16:46 ` Sean Christopherson
2022-03-04 19:48 ` [RFC PATCH v5 004/104] KVM: Enable hardware before doing arch VM initialization isaku.yamahata
2022-03-13 14:00 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 005/104] KVM: x86: Refactor KVM VMX module init/exit functions isaku.yamahata
2022-03-13 13:54 ` Paolo Bonzini
2022-03-14 19:22 ` Isaku Yamahata
2022-03-04 19:48 ` [RFC PATCH v5 006/104] KVM: TDX: Add placeholders for TDX VM/vcpu structure isaku.yamahata
2022-03-13 13:55 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 007/104] x86/virt/tdx: Add a helper function to return system wide info about TDX module isaku.yamahata
2022-03-13 13:59 ` Paolo Bonzini
2022-03-13 23:02 ` Kai Huang
2022-03-04 19:48 ` [RFC PATCH v5 008/104] KVM: TDX: Add a function to initialize " isaku.yamahata
2022-03-13 14:03 ` Paolo Bonzini
2022-03-14 19:45 ` Isaku Yamahata
2022-03-31 0:03 ` Sean Christopherson
2022-03-31 1:02 ` Kai Huang
2022-03-31 17:03 ` Isaku Yamahata
2022-03-31 19:34 ` Sean Christopherson
[not found] ` <20220401032741.GA2806@gao-cwp>
2022-04-01 5:07 ` Chao Gao
2022-03-31 3:31 ` Kai Huang
2022-03-31 19:41 ` Isaku Yamahata
2022-04-01 6:56 ` Xiaoyao Li
2022-04-01 20:18 ` Isaku Yamahata
2022-04-02 2:40 ` Xiaoyao Li
2022-03-04 19:48 ` [RFC PATCH v5 009/104] KVM: x86: Introduce vm_type to differentiate default VMs from confidential VMs isaku.yamahata
2022-03-13 14:07 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 010/104] KVM: TDX: Make TDX VM type supported isaku.yamahata
2022-03-13 23:08 ` Kai Huang
2022-03-15 21:03 ` Isaku Yamahata
2022-03-15 21:47 ` Kai Huang
2022-03-15 21:49 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 011/104] [MARKER] The start of TDX KVM patch series: TDX architectural definitions isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 012/104] KVM: TDX: Define " isaku.yamahata
2022-03-13 14:30 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 013/104] KVM: TDX: Add TDX "architectural" error codes isaku.yamahata
2022-03-13 14:08 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 014/104] KVM: TDX: Add a function for KVM to invoke SEAMCALL isaku.yamahata
2022-03-13 14:10 ` Paolo Bonzini
2022-03-13 22:42 ` Kai Huang
2022-03-04 19:48 ` [RFC PATCH v5 015/104] KVM: TDX: add a helper function for KVM to issue SEAMCALL isaku.yamahata
2022-03-13 14:11 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 016/104] KVM: TDX: Add C wrapper functions for SEAMCALLs to the TDX module isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 017/104] KVM: TDX: Add helper functions to print TDX SEAMCALL error isaku.yamahata
2022-03-13 14:12 ` Paolo Bonzini
2022-04-15 16:54 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 018/104] [MARKER] The start of TDX KVM patch series: TD VM creation/destruction isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 019/104] KVM: TDX: Stub in tdx.h with structs, accessors, and VMCS helpers isaku.yamahata
2022-04-15 16:55 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 020/104] KVM: TDX: allocate per-package mutex isaku.yamahata
2022-04-05 12:39 ` Paolo Bonzini
2022-04-08 0:44 ` Isaku Yamahata
2022-03-04 19:48 ` [RFC PATCH v5 021/104] KVM: x86: Introduce hooks to free VM callback prezap and vm_free isaku.yamahata
2022-03-31 3:02 ` Kai Huang
2022-03-31 19:54 ` Isaku Yamahata
2022-04-05 12:40 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 022/104] KVM: Add max_vcpus field in common 'struct kvm' isaku.yamahata
2022-04-05 12:42 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 023/104] x86/cpu: Add helper functions to allocate/free MKTME keyid isaku.yamahata
2022-03-31 1:21 ` Kai Huang
2022-03-31 20:15 ` Isaku Yamahata
2022-04-06 1:55 ` Kai Huang
2022-04-07 1:00 ` Kai Huang
2022-04-05 13:08 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 024/104] KVM: TDX: create/destroy VM structure isaku.yamahata
2022-03-31 4:17 ` Kai Huang
2022-03-31 22:12 ` Isaku Yamahata
2022-03-31 23:41 ` Kai Huang
2022-04-05 12:44 ` Paolo Bonzini
2022-04-08 0:51 ` Isaku Yamahata
2022-04-15 13:47 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 025/104] KVM: TDX: Add place holder for TDX VM specific mem_enc_op ioctl isaku.yamahata
2022-04-05 12:50 ` Paolo Bonzini
2022-04-08 0:56 ` Isaku Yamahata
2022-03-04 19:48 ` [RFC PATCH v5 026/104] KVM: TDX: x86: Add vm ioctl to get TDX systemwide parameters isaku.yamahata
2022-04-05 12:52 ` Paolo Bonzini
2022-04-06 1:54 ` Xiaoyao Li
2022-04-07 1:07 ` Kai Huang
2022-04-07 1:17 ` Xiaoyao Li
2022-04-08 0:58 ` Isaku Yamahata
2022-03-04 19:48 ` [RFC PATCH v5 027/104] KVM: TDX: initialize VM with TDX specific parameters isaku.yamahata
2022-03-31 4:55 ` Kai Huang
2022-04-05 13:01 ` Paolo Bonzini
2022-04-06 2:06 ` Xiaoyao Li
2022-04-06 11:27 ` Paolo Bonzini
2022-04-08 2:18 ` Isaku Yamahata
2022-04-05 12:58 ` Paolo Bonzini
2022-04-07 1:29 ` Xiaoyao Li
2022-04-07 1:51 ` Kai Huang
2022-04-08 3:33 ` Isaku Yamahata
2022-03-04 19:48 ` [RFC PATCH v5 028/104] [MARKER] The start of TDX KVM patch series: TD vcpu creation/destruction isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 029/104] KVM: TDX: allocate/free TDX vcpu structure isaku.yamahata
2022-04-05 13:04 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 030/104] KVM: TDX: Do TDX specific vcpu initialization isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 031/104] [MARKER] The start of TDX KVM patch series: KVM MMU GPA stolen bits isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 032/104] KVM: x86/mmu: introduce config for PRIVATE KVM MMU isaku.yamahata
2022-03-31 11:23 ` Kai Huang
2022-04-01 1:51 ` Isaku Yamahata
2022-04-01 2:13 ` Kai Huang
2022-04-05 13:48 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 033/104] KVM: x86: Add infrastructure for stolen GPA bits isaku.yamahata
2022-03-31 11:16 ` Kai Huang
2022-04-01 2:10 ` Kai Huang
2022-04-01 2:34 ` Isaku Yamahata
2022-04-05 14:02 ` Paolo Bonzini
2022-04-05 14:02 ` Paolo Bonzini
2022-04-05 13:55 ` Paolo Bonzini
2022-04-06 2:23 ` Kai Huang
2022-04-06 11:26 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 034/104] [MARKER] The start of TDX KVM patch series: KVM TDP refactoring for TDX isaku.yamahata
2022-03-04 19:48 ` [RFC PATCH v5 035/104] KVM: x86/mmu: Disallow dirty logging for x86 TDX isaku.yamahata
2022-04-05 13:09 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 036/104] KVM: x86/mmu: Explicitly check for MMIO spte in fast page fault isaku.yamahata
2022-04-05 13:17 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 037/104] KVM: x86/mmu: Allow non-zero init value for shadow PTE isaku.yamahata
2022-04-01 5:13 ` Kai Huang
2022-04-01 7:13 ` Kai Huang
2022-04-05 14:14 ` Paolo Bonzini
2022-04-08 18:38 ` Isaku Yamahata
2022-04-05 14:13 ` Paolo Bonzini
2022-04-05 14:10 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 038/104] KVM: x86/mmu: Allow per-VM override of the TDP max page level isaku.yamahata
2022-04-01 5:15 ` Kai Huang
2022-04-01 14:08 ` Sean Christopherson
2022-04-01 20:28 ` Isaku Yamahata
2022-04-01 20:53 ` Sean Christopherson
2022-04-01 22:27 ` Kai Huang
2022-04-02 0:08 ` Sean Christopherson
2022-04-04 0:41 ` Kai Huang
2022-03-04 19:48 ` [RFC PATCH v5 039/104] KVM: x86/mmu: Disallow fast page fault on private GPA isaku.yamahata
2022-04-05 13:22 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 040/104] KVM: VMX: Split out guts of EPT violation to common/exposed function isaku.yamahata
2022-04-05 14:43 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 041/104] KVM: VMX: Move setting of EPT MMU masks to common VT-x code isaku.yamahata
2022-04-05 14:48 ` Paolo Bonzini
2022-03-04 19:48 ` [RFC PATCH v5 042/104] KVM: x86/mmu: Track shadow MMIO value/mask on a per-VM basis isaku.yamahata
2022-04-05 15:25 ` Paolo Bonzini
2022-04-08 18:46 ` Isaku Yamahata
2022-04-19 19:55 ` Sean Christopherson
2022-04-06 11:06 ` Kai Huang
2022-04-07 3:05 ` Kai Huang
2022-04-08 19:12 ` Isaku Yamahata
2022-04-08 23:34 ` Kai Huang
2022-03-04 19:48 ` [RFC PATCH v5 043/104] KVM: TDX: Add load_mmu_pgd method for TDX isaku.yamahata
2022-04-05 14:51 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 044/104] [MARKER] The start of TDX KVM patch series: KVM TDP MMU hooks isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 045/104] KVM: x86/tdp_mmu: make REMOVED_SPTE include shadow_initial value isaku.yamahata
2022-04-05 14:22 ` Paolo Bonzini
2022-04-06 23:35 ` Sean Christopherson
2022-04-07 13:52 ` Paolo Bonzini
2022-04-06 23:30 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 046/104] KVM: x86/tdp_mmu: refactor kvm_tdp_mmu_map() isaku.yamahata
2022-04-05 14:53 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 047/104] KVM: x86/mmu: add a private pointer to struct kvm_mmu_page isaku.yamahata
2022-04-05 14:58 ` Paolo Bonzini
2022-04-06 23:43 ` Kai Huang
2022-04-07 13:52 ` Paolo Bonzini
2022-04-07 22:53 ` Kai Huang
2022-04-07 23:03 ` Paolo Bonzini
2022-04-07 23:24 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 048/104] KVM: x86/tdp_mmu: Support TDX private mapping for TDP MMU isaku.yamahata
2022-04-07 0:50 ` Kai Huang
2022-04-25 19:10 ` Sagi Shahar
2022-04-26 21:12 ` Isaku Yamahata
2022-04-29 0:28 ` Sagi Shahar
2022-04-29 0:46 ` Sean Christopherson
2022-03-04 19:49 ` [RFC PATCH v5 049/104] KVM: x86/tdp_mmu: Ignore unsupported mmu operation on private GFNs isaku.yamahata
2022-04-05 15:15 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 050/104] [MARKER] The start of TDX KVM patch series: TDX EPT violation isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 051/104] KVM: TDX: TDP MMU TDX support isaku.yamahata
2022-04-07 2:20 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 052/104] [MARKER] The start of TDX KVM patch series: KVM TDP MMU MapGPA isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 053/104] KVM: x86/mmu: steal software usable bit for EPT to represent shared page isaku.yamahata
2022-04-15 15:21 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 054/104] KVM: x86/tdp_mmu: Keep PRIVATE_PROHIBIT bit when zapping isaku.yamahata
2022-04-07 1:43 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 055/104] KVM: x86/tdp_mmu: prevent private/shared map based on PRIVATE_PROHIBIT isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 056/104] KVM: x86/tdp_mmu: implement MapGPA hypercall for TDX isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 057/104] KVM: x86/mmu: Introduce kvm_mmu_map_tdp_page() for use by TDX isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 058/104] KVM: x86/mmu: Focibly use TDP MMU for TDX isaku.yamahata
2022-04-07 1:49 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 059/104] [MARKER] The start of TDX KVM patch series: TD finalization isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 060/104] KVM: TDX: Create initial guest memory isaku.yamahata
2022-04-07 2:30 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 061/104] KVM: TDX: Finalize VM initialization isaku.yamahata
2022-04-15 13:52 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 062/104] [MARKER] The start of TDX KVM patch series: TD vcpu enter/exit isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 063/104] KVM: TDX: Add helper assembly function to TDX vcpu isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 064/104] KVM: TDX: Implement TDX vcpu enter/exit path isaku.yamahata
2022-03-22 17:28 ` Erdem Aktas
2022-03-23 17:55 ` Isaku Yamahata
2022-03-23 20:05 ` Erdem Aktas
2022-03-23 22:48 ` Isaku Yamahata
2022-03-04 19:49 ` [RFC PATCH v5 065/104] KVM: TDX: vcpu_run: save/restore host state(host kernel gs) isaku.yamahata
2022-04-15 13:56 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 066/104] KVM: TDX: restore host xsave state when exit from the guest TD isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 067/104] KVM: x86: Allow to update cached values in kvm_user_return_msrs w/o wrmsr isaku.yamahata
2022-04-15 14:02 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 068/104] KVM: TDX: restore user ret MSRs isaku.yamahata
2022-04-15 14:06 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 069/104] [MARKER] The start of TDX KVM patch series: TD vcpu exits/interrupts/hypercalls isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 070/104] KVM: TDX: complete interrupts after tdexit isaku.yamahata
2022-04-15 14:07 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 071/104] KVM: TDX: restore debug store when TD exit isaku.yamahata
2022-04-15 14:20 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 072/104] KVM: TDX: handle vcpu migration over logical processor isaku.yamahata
2022-04-15 14:14 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 073/104] KVM: TDX: track LP tdx vcpu run and teardown vcpus on descroing the guest TD isaku.yamahata
2022-03-23 0:54 ` Erdem Aktas
2022-03-23 19:08 ` Isaku Yamahata
2022-03-23 20:17 ` Erdem Aktas
2022-03-04 19:49 ` [RFC PATCH v5 074/104] KVM: x86: Add a switch_db_regs flag to handle TDX's auto-switched behavior isaku.yamahata
2022-04-05 15:32 ` Paolo Bonzini
2022-04-06 23:28 ` Sean Christopherson
2022-03-04 19:49 ` [RFC PATCH v5 075/104] KVM: x86: Check for pending APICv interrupt in kvm_vcpu_has_events() isaku.yamahata
2022-04-08 16:24 ` Sean Christopherson
2022-04-15 14:20 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 076/104] KVM: x86: Add option to force LAPIC expiration wait isaku.yamahata
2022-04-05 15:33 ` Paolo Bonzini
2022-04-08 16:36 ` Sean Christopherson
2022-03-04 19:49 ` [RFC PATCH v5 077/104] KVM: TDX: Use vcpu_to_pi_desc() uniformly in posted_intr.c isaku.yamahata
2022-04-05 15:36 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 078/104] KVM: TDX: Implement interrupt injection isaku.yamahata
2022-04-06 11:47 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 079/104] KVM: TDX: Implements vcpu request_immediate_exit isaku.yamahata
2022-04-06 12:49 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 080/104] KVM: TDX: Implement methods to inject NMI isaku.yamahata
2022-04-06 12:47 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 081/104] KVM: VMX: Modify NMI and INTR handlers to take intr_info as function argument isaku.yamahata
2022-04-06 12:49 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 082/104] KVM: VMX: Move NMI/exception handler to common helper isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 083/104] KVM: x86: Split core of hypercall emulation to helper function isaku.yamahata
2022-03-21 18:32 ` Sagi Shahar
2022-03-23 17:53 ` Isaku Yamahata
2022-04-07 13:12 ` Paolo Bonzini
2022-04-08 5:34 ` Isaku Yamahata
2022-03-04 19:49 ` [RFC PATCH v5 084/104] KVM: TDX: Add a place holder to handle TDX VM exit isaku.yamahata
2022-04-15 14:20 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 085/104] KVM: TDX: handle EXIT_REASON_OTHER_SMI isaku.yamahata
2022-04-15 14:29 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 086/104] KVM: TDX: handle ept violation/misconfig exit isaku.yamahata
2022-04-06 20:50 ` Sagi Shahar
2022-04-07 1:09 ` Xiaoyao Li
2022-03-04 19:49 ` [RFC PATCH v5 087/104] KVM: TDX: handle EXCEPTION_NMI and EXTERNAL_INTERRUPT isaku.yamahata
2022-04-15 14:49 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 088/104] KVM: TDX: Add TDG.VP.VMCALL accessors to access guest vcpu registers isaku.yamahata
2022-04-07 4:06 ` Kai Huang
2022-04-15 14:50 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 089/104] KVM: TDX: Add a placeholder for handler of TDX hypercalls (TDG.VP.VMCALL) isaku.yamahata
2022-04-07 4:15 ` Kai Huang
2022-04-07 13:14 ` Paolo Bonzini
2022-04-07 14:39 ` Sean Christopherson
2022-04-07 18:04 ` Paolo Bonzini
2022-04-07 18:11 ` Sean Christopherson
2022-04-07 23:20 ` Kai Huang
2022-03-04 19:49 ` [RFC PATCH v5 090/104] KVM: TDX: handle KVM hypercall with TDG.VP.VMCALL isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 091/104] KVM: TDX: Handle TDX PV CPUID hypercall isaku.yamahata
2022-04-07 13:16 ` Paolo Bonzini
2022-04-07 14:48 ` Sean Christopherson
2022-04-07 18:03 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 092/104] KVM: TDX: Handle TDX PV HLT hypercall isaku.yamahata
2022-04-07 13:56 ` Paolo Bonzini
2022-04-07 15:02 ` Sean Christopherson
2022-04-07 15:56 ` Paolo Bonzini
2022-04-07 16:08 ` Sean Christopherson
2022-04-08 4:58 ` Isaku Yamahata
2022-04-08 9:57 ` Paolo Bonzini
2022-04-08 14:51 ` Sean Christopherson
2022-04-11 17:40 ` Paolo Bonzini
2022-04-14 17:09 ` Sean Christopherson
2022-04-07 14:51 ` Sean Christopherson
2022-03-04 19:49 ` [RFC PATCH v5 093/104] KVM: TDX: Handle TDX PV port io hypercall isaku.yamahata
2022-04-15 14:59 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 094/104] KVM: TDX: Handle TDX PV MMIO hypercall isaku.yamahata
2022-04-15 15:05 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 095/104] KVM: TDX: Implement callbacks for MSR operations for TDX isaku.yamahata
2022-04-15 15:07 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 096/104] KVM: TDX: Handle TDX PV rdmsr hypercall isaku.yamahata
2022-04-15 15:08 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 097/104] KVM: TDX: Handle TDX PV wrmsr hypercall isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 098/104] KVM: TDX: Handle TDX PV report fatal error hypercall isaku.yamahata
2022-04-15 15:13 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 099/104] KVM: TDX: Handle TDX PV map_gpa hypercall isaku.yamahata
2022-03-04 19:49 ` [RFC PATCH v5 100/104] KVM: TDX: Silently discard SMI request isaku.yamahata
2022-04-05 15:41 ` Paolo Bonzini
2022-03-04 19:49 ` [RFC PATCH v5 101/104] KVM: TDX: Silently ignore INIT/SIPI isaku.yamahata
2022-04-05 15:48 ` Paolo Bonzini
2022-04-05 17:53 ` Tom Lendacky
2022-04-07 11:09 ` Xiaoyao Li
2022-04-07 12:12 ` Paolo Bonzini
2022-04-08 3:40 ` Isaku Yamahata
2022-03-04 19:49 ` isaku.yamahata [this message]
2022-04-05 15:56 ` [RFC PATCH v5 102/104] KVM: TDX: Add methods to ignore accesses to CPU state Paolo Bonzini
2022-04-08 3:50 ` Isaku Yamahata
2022-04-12 6:49 ` Xiaoyao Li
2022-04-12 6:52 ` Paolo Bonzini
2022-04-12 7:31 ` Xiaoyao Li
2022-03-04 19:49 ` [RFC PATCH v5 103/104] Documentation/virtual/kvm: Document on Trust Domain Extensions(TDX) isaku.yamahata
2022-03-04 19:50 ` [RFC PATCH v5 104/104] KVM: x86: design documentation on TDX support of x86 KVM TDP MMU isaku.yamahata
2022-03-07 7:44 ` [RFC PATCH v5 000/104] KVM TDX basic feature support Christoph Hellwig
2022-03-13 14:00 ` Paolo Bonzini
2022-04-15 15:18 ` Paolo Bonzini
2022-04-15 17:05 ` Paolo Bonzini
2022-04-15 21:19 ` Isaku Yamahata
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