From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4318C43334 for ; Mon, 3 Sep 2018 20:38:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 859BB2086B for ; Mon, 3 Sep 2018 20:38:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 859BB2086B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=buserror.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728516AbeIDBAO (ORCPT ); Mon, 3 Sep 2018 21:00:14 -0400 Received: from baldur.buserror.net ([165.227.176.147]:60768 "EHLO baldur.buserror.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727501AbeIDBAO (ORCPT ); Mon, 3 Sep 2018 21:00:14 -0400 Received: from [2601:449:8400:7293:12bf:48ff:fe84:c9a0] by baldur.buserror.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1fwvXU-0004dS-Mm; Mon, 03 Sep 2018 15:33:39 -0500 Message-ID: <3a4274af2200923875ff05f945888a34d6dccee3.camel@buserror.net> From: Scott Wood To: Andy Tang , Vabhav Sharma , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "rjw@rjwysocki.net" , "viresh.kumar@linaro.org" , "linux-clk@vger.kernel.org" , "linux-pm@vger.kernel.org" , "linux-kernel-owner@vger.kernel.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "gregkh@linuxfoundation.org" , "arnd@arndb.de" , "kstewart@linuxfoundation.org" , "yamada.masahiro@socionext.com" Cc: Yogesh Narayan Gaur , "linux@armlinux.org.uk" , Udit Kumar , Varun Sethi Date: Mon, 03 Sep 2018 15:33:33 -0500 In-Reply-To: References: <1534747636-20064-1-git-send-email-vabhav.sharma@nxp.com> <1534747636-20064-4-git-send-email-vabhav.sharma@nxp.com> <4a9ea6b451683ec98c92e86a5ae6b91213a6afcf.camel@buserror.net> Organization: Red Hat Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2601:449:8400:7293:12bf:48ff:fe84:c9a0 X-SA-Exim-Rcpt-To: andy.tang@nxp.com, vabhav.sharma@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de, kstewart@linuxfoundation.org, yamada.masahiro@socionext.com, yogeshnarayan.gaur@nxp.com, linux@armlinux.org.uk, udit.kumar@nxp.com, V.Sethi@nxp.com X-SA-Exim-Mail-From: oss@buserror.net Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on baldur.buserror.net) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2018-09-03 at 01:17 +0000, Andy Tang wrote: > Hi Scott, > > Please see my replay in line. > > > -----Original Message----- > > From: Linuxppc-dev > > On > > Behalf Of Scott Wood > > Sent: 2018年9月1日 4:29 > > To: Andy Tang ; Vabhav Sharma > > ; linux-kernel@vger.kernel.org; > > devicetree@vger.kernel.org; robh+dt@kernel.org; > > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org; > > linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com; > > sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org; > > linux-clk@vger.kernel.org; linux-pm@vger.kernel.org; > > linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com; > > will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de; > > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com > > Cc: Yogesh Narayan Gaur ; > > linux@armlinux.org.uk; Udit Kumar ; Varun Sethi > > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for > > lx2160a > > > > On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote: > > > We don't want to increase NUM_CMUX each time new soc with more > > > > cmuxes added. > > > > You don't want to have to make a trivial change each time you exceed a > > limit that has yet to be exceeded once since NUM_CMUX was added? > > This isn't ABI or in any other way hard to change. It's right in the same > > file > > as the chip description you'd be adding. > > > > And even if a chip did come along with 16 cmuxes, you'd then need to > > increase the array to 17 to hold the -1 if you don't want to leave a > > situation > > like the > > p4080 is in now, where a chip's cmux array could be broken by increasing > > NUM_CMUX further. > > > > [Andy] Adding buffer to a limitation number is always a good habit when > coding. We often forget to increase this value when > a new chip with more cmuxes added. "often"? There has never been a new chip added with more cmuxes than p4080's 8, and if one does come along and you forget, the compiler should complain about exceeding the array length with a static initializer. This isn't like an array that is filled with a runtime-determined length. > Like this patch, we didn't increase this value at first. We spent a lot of > time finding out that NUM_CMUX needs to be increased too. Are you talking about some other chip that you haven't sent a patch for yet? Or is the cmux array for this chip wrong? What specifically did you see happen "at first"? > It is a personal preference how to set this value. I think it is better to > increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue > even though it is a trivial change. And I agree the description needs to be > updated. I'm not the clock maintainer, so it's not up to me, but I don't see the point in setting it to an arbitrary number, and I do not agree that increasing NUM_CMUX is a suitable replacement for NUM_CMUX+1 in cmux_to_group[], as that array should be one larger than cmux[] in order to allow every chip to have a -1 terminator. In any case, any change to NUM_CMUX should be a separate patch because it's not required for lx2160a support (assuming lx2160a was correctly described by this patch). -Scott