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[83.9.32.99]) by smtp.gmail.com with ESMTPSA id i2-20020a05651c120200b002935305ff4asm643079lja.82.2023.02.27.00.43.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 00:43:16 -0800 (PST) Message-ID: <3aa78b15-8e6c-9657-0d08-0d0452d51fbe@linaro.org> Date: Mon, 27 Feb 2023 09:43:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 1/6] dt-bindings: arm-smmu: Use qcom,smmu compatible for MMU500 adreno SMMUs To: Rob Herring Cc: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, marijn.suijten@somainline.org, Will Deacon , Robin Murphy , Joerg Roedel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230217111613.306978-1-konrad.dybcio@linaro.org> <20230226173706.GA60188-robh@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20230226173706.GA60188-robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26.02.2023 18:37, Rob Herring wrote: > On Fri, Feb 17, 2023 at 12:16:08PM +0100, Konrad Dybcio wrote: >> qcom,smmu-500 was introduced to prevent people from adding new >> compatibles for what seems to roughly be the same hardware. Use it for >> qcom,adreno-smmu-compatible targets as well. >> >> Signed-off-by: Konrad Dybcio >> --- >> v1 -> v2: >> - Add this patch, omitted previously (big oops) >> >> .../devicetree/bindings/iommu/arm,smmu.yaml | 14 ++++++++++++-- >> 1 file changed, 12 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> index 807cb511fe18..4d7f61700cae 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> @@ -75,9 +75,19 @@ properties: >> - qcom,sm8350-smmu-500 >> - qcom,sm8450-smmu-500 >> - const: arm,mmu-500 >> - >> - - description: Qcom Adreno GPUs implementing "arm,smmu-500" >> + - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,smmu-500" >> + items: >> + - enum: >> + - qcom,sc7280-smmu-500 >> + - qcom,sm8150-smmu-500 >> + - qcom,sm8250-smmu-500 >> + - const: qcom,adreno-smmu >> + - const: qcom,smmu-500 >> + - const: arm,mmu-500 > > 4 compatibles seems excessive. Is adding one that helpful? Is > 'arm,mmu-500' useful on its own? Yes. per-soc compatible is there for per-soc quirks should there be any qcom,adreno-smmu enabled per-process pagetables qcom,smmu-500 matches the qcom smmu implementation arm,mmu-500 matches the smmu driver as a whole > >> + - description: Qcom Adreno GPUs implementing "arm,smmu-500" (legacy binding) > > Perhaps fix the existing typo: arm,mmu-500 Ack Konrad > >> + deprecated: true >> items: >> + # Do not add additional SoC to this list. Instead use previous list. >> - enum: >> - qcom,sc7280-smmu-500 >> - qcom,sm8150-smmu-500 >> -- >> 2.39.1 >>