From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD2F8C71155 for ; Mon, 30 Nov 2020 23:17:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 839BD2076E for ; Mon, 30 Nov 2020 23:17:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728651AbgK3XRX (ORCPT ); Mon, 30 Nov 2020 18:17:23 -0500 Received: from mga03.intel.com ([134.134.136.65]:14641 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725980AbgK3XRX (ORCPT ); Mon, 30 Nov 2020 18:17:23 -0500 IronPort-SDR: 2M66a1CBDUX2xv1RrxEuV7pYVhO0OMukquy7cf1L3M9fl4zADSbLKV8BAfGdBFGNlBwNUm43EX MNPXFz8x/nOA== X-IronPort-AV: E=McAfee;i="6000,8403,9821"; a="172827551" X-IronPort-AV: E=Sophos;i="5.78,382,1599548400"; d="scan'208";a="172827551" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2020 15:16:42 -0800 IronPort-SDR: 8zNcFY7NhPl0VCOSeKl8PZxj5MKCbmm2A/J0IdXrJVCPnhKSv9Tcuho0ZMivcKfzjSj1RDIlJG /oGpjHi+WO/g== X-IronPort-AV: E=Sophos;i="5.78,382,1599548400"; d="scan'208";a="480848257" Received: from yyu32-mobl1.amr.corp.intel.com (HELO [10.212.122.22]) ([10.212.122.22]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2020 15:16:40 -0800 Subject: Re: [NEEDS-REVIEW] [PATCH v15 03/26] x86/fpu/xstate: Introduce CET MSR XSAVES supervisor states To: Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang , Pengfei Xu References: <20201110162211.9207-1-yu-cheng.yu@intel.com> <20201110162211.9207-4-yu-cheng.yu@intel.com> From: "Yu, Yu-cheng" Message-ID: <3b83517e-17d6-3b53-6dbf-8ad727707b16@intel.com> Date: Mon, 30 Nov 2020 15:16:39 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/30/2020 9:45 AM, Dave Hansen wrote: > On 11/10/20 8:21 AM, Yu-cheng Yu wrote: >> Control-flow Enforcement Technology (CET) adds five MSRs. Introduce >> them and their XSAVES supervisor states: >> >> MSR_IA32_U_CET (user-mode CET settings), >> MSR_IA32_PL3_SSP (user-mode Shadow Stack pointer), >> MSR_IA32_PL0_SSP (kernel-mode Shadow Stack pointer), >> MSR_IA32_PL1_SSP (Privilege Level 1 Shadow Stack pointer), >> MSR_IA32_PL2_SSP (Privilege Level 2 Shadow Stack pointer). > > This patch goes into a bunch of XSAVE work that this changelog only > briefly touches on. I think it needs to be beefed up a bit. > [...] > > Do we have any other spots in the kernel where we care about: > > boot_cpu_has(X86_FEATURE_SHSTK) || > boot_cpu_has(X86_FEATURE_IBT) > > ? If so, we could also address this by declaring a software-defined > X86_FEATURE_CET and then setting it if SHSTK||IBT is supported, then we > just put that one feature in xsave_cpuid_features[]. > These features have different CPUIDs but are complementary parts. I don't know if someday there will be shadow-stack-only CPUs, but an IBT-only CPU is weird. What if the kernel checks that the CPU has both features and presents only one feature flag (X86_FEATURE_CET), no X86_FEATURE_SHSTK or X86_FEATURE_IBT?