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[86.30.250.44]) by smtp.googlemail.com with ESMTPSA id t69sm4002749wmt.16.2019.03.13.11.29.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:29:41 -0700 (PDT) Subject: Re: [PATCH v2] PCI: qcom: Use default config space read function To: Marc Gonzalez , Stanimir Varbanov , Bjorn Helgaas Cc: Andy Gross , David Brown , Bjorn Andersson , PCI , MSM , LKML , Jeffrey Hugo References: <94bb3f22-c5a7-1891-9d89-42a520e9a592@free.fr> <65321fe3-ca29-c454-63ae-98a46c2e5158@mm-sol.com> <1205cbfb-ac06-63a5-9401-75d4e68b15b5@free.fr> <38ad143b-3b07-4d19-8ccd-ca39fb51e53d@free.fr> <7d3d788a-d6a3-a70b-adab-6c65771cacc4@free.fr> From: Srinivas Kandagatla Message-ID: <3c76613e-e60d-94b8-dd6f-b8f4e1928263@linaro.org> Date: Wed, 13 Mar 2019 18:29:40 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <7d3d788a-d6a3-a70b-adab-6c65771cacc4@free.fr> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 13/03/2019 11:45, Marc Gonzalez wrote: > We don't need to fudge the device class in qcom_pcie_rd_own_conf() > because dw_pcie_setup_rc() already does the right thing: > > /* Program correct class for RC */ > dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); > > Signed-off-by: Marc Gonzalez > --- > Changes from v1 to v2: Completely drop qcom_pcie_rd_own_conf > Srinivas, could you test this patch on apq/ipq8064? > --- > drivers/pci/controller/dwc/pcie-qcom.c | 17 ----------------- > 1 file changed, 17 deletions(-) > I tried this patch on IFC6410 board which has APQ8064, and the pci does not work anymore after applying this patch. non-working output of 'lspci -vvv' https://paste.ubuntu.com/p/ndmdsW4zkJ/ and bootlog ahttps://paste.ubuntu.com/p/CqVzGymnq8/ working without patch : https://paste.ubuntu.com/p/TJm4hgjGW4/ I have not debugged it any further other than just testing the patch. Let me know if you need any more dumps for more debug. Thanks, srini > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 3de5510fd3d5..d0c5c7616b3e 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1131,25 +1131,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp) > return ret; > } > > -static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > - u32 *val) > -{ > - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > - > - /* the device class is not reported correctly from the register */ > - if (where == PCI_CLASS_REVISION && size == 4) { > - *val = readl(pci->dbi_base + PCI_CLASS_REVISION); > - *val &= 0xff; /* keep revision id */ > - *val |= PCI_CLASS_BRIDGE_PCI << 16; > - return PCIBIOS_SUCCESSFUL; > - } > - > - return dw_pcie_read(pci->dbi_base + where, size, val); > -} > - > static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { > .host_init = qcom_pcie_host_init, > - .rd_own_conf = qcom_pcie_rd_own_conf, > }; > > /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ >