From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F3F4C433E2 for ; Mon, 15 Jun 2020 19:09:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 402F120739 for ; Mon, 15 Jun 2020 19:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731441AbgFOTJy (ORCPT ); Mon, 15 Jun 2020 15:09:54 -0400 Received: from foss.arm.com ([217.140.110.172]:54004 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731372AbgFOTJy (ORCPT ); Mon, 15 Jun 2020 15:09:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 087711FB; Mon, 15 Jun 2020 12:09:52 -0700 (PDT) Received: from [10.57.9.128] (unknown [10.57.9.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F2D9C3F6CF; Mon, 15 Jun 2020 12:09:49 -0700 (PDT) Subject: Re: [PATCH v2] spi: bcm2835: Enable shared interrupt support To: Lukas Wunner Cc: Florian Fainelli , Mark Brown , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Scott Branden , Ray Jui , linux-kernel@vger.kernel.org, "open list:SPI SUBSYSTEM" , Rob Herring , "maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE..." , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , Martin Sperl , Nicolas Saenz Julienne References: <20200604212819.715-1-f.fainelli@gmail.com> <142d48ae-2725-1368-3e11-658449662371@arm.com> <20200605132037.GF5413@sirena.org.uk> <2e371a32-fb52-03a2-82e4-5733d9f139cc@arm.com> <06342e88-e130-ad7a-9f97-94f09156f868@arm.com> <20200608114148.4bau4mdcvwgf25ut@wunner.de> From: Robin Murphy Message-ID: <3d4fd3f9-9bde-90a8-bef5-9fc97cc9b363@arm.com> Date: Mon, 15 Jun 2020 20:09:48 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200608114148.4bau4mdcvwgf25ut@wunner.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020-06-08 12:41, Lukas Wunner wrote: > On Mon, Jun 08, 2020 at 12:11:11PM +0100, Robin Murphy wrote: >> And all in code that has at least one obvious inefficiency left on >> the table either way. > > Care to submit a patch to overcome that inefficiency? I'll have a quick go, but without any way to measure performance impact (or even test for correctness) I don't fancy going too deep based purely on disassembly and ARM11 cycle timings. >> This thread truly epitomises Knuth's "premature optimisation" quote... ;) > > The thread came about because it can be determined at compile time > whether the interrupt is going to be shared: ...which is exactly my point - "because it can be" is anything but proof that avoiding a trivial check makes enough measurable difference to justify putting in the effort to do so. > On the BCM2835 (Raspberry Pi 1), CONFIG_ARCH_MULTI_V6 is set and this > SoC doesn't have multiple bcm2835-spi instances, so no shared interrupt. > > The question is how to discern BCM2836/BCM2837 (Raspberry Pi 2/3), which > do not have multiple instances, and BCM2711 (Raspberry Pi 4) which does. Hmm, how much relative importance does that have? On a 700MHz ARM11 it's obviously desirable to spend as little time in the IRQ handler as possible in order to have time left to do anything else, but on the other SoCs even if the IRQ remains permanently asserted it can still only consume 25% of the available CPU capacity, at which point the impact of 2-3 cycles either way at 1GHz+ seems pretty much immeasurable. > The Raspberry Pi Foundation compiles BCM2711 kernels with CONFIG_ARM_LPAE=y, > but Florian considered that kludgy as a discriminator and opted for > runtime-detection via the compatible string instead. If you've got > a better idea please come forward. > > Is "optimize shared IRQ support away if IS_ENABLED(CONFIG_ARCH_MULTI_V6), > else leave it in" the best we can do? In all honesty I'm starting to think it seriously might be :) Robin.