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From: Richard Genoud <richard.genoud@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Willy Tarreau <w@1wt.eu>,
	linux-kernel@vger.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Gregory CLEMENT <gregory.clement@bootlin.com>,
	Yelena Krivosheev <yelena@marvell.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	netdev@vger.kernel.org
Subject: Re: CRC errors between mvneta and macb
Date: Tue, 23 Oct 2018 08:58:10 +0200	[thread overview]
Message-ID: <3d967432-b526-0cee-ed45-beb27bebd031@sorico.fr> (raw)
In-Reply-To: <20181022181918.GF24112@lunn.ch>

Le 22/10/2018 à 20:19, Andrew Lunn a écrit :
>> I dug more on the subject, and I think I found what Marvell's PHY/MAC
>> doesn't like.
> 
> Hi Richard
> 
> What PHY is being used?
> 
88E1512-NNP2

>> After analyzing the ethernet frame on the Davicom PHY's output (pin
>> TX+), I find out that the FCS errors occurs when the ethernet preamble
>> is longer than 56bits. (something like 58 or 60 bits)
> 
> Some Marvell PHYs have a register bit which might be of interest: Page
> 2, register 16, bit 6.
> 
> 0 = Pad odd nibble preambles in copper receive packets.
> 1 = Pass as is and do not pad odd nibble preambles in
> 
>   Andrew
> 

Thanks, I'll look into that.

Richard

  reply	other threads:[~2018-10-23  6:58 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-19 15:15 Richard Genoud
2018-10-19 15:44 ` Willy Tarreau
2018-10-22  6:51   ` Richard Genoud
2018-10-22 15:15     ` Richard Genoud
2018-10-22 16:34       ` Willy Tarreau
2018-10-23  6:56         ` Richard Genoud
2018-10-22 18:19       ` Andrew Lunn
2018-10-23  6:58         ` Richard Genoud [this message]
2018-10-23 12:37         ` Richard Genoud

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