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From: Russ Weight <russell.h.weight@intel.com>
To: Tom Rix <trix@redhat.com>,
	mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com,
	matthew.gerlach@intel.com
Subject: Re: [PATCH v1 07/12] fpga: expose sec-mgr update status
Date: Tue, 22 Sep 2020 15:31:10 -0700	[thread overview]
Message-ID: <3dc77b88-8d6c-424e-3c6e-a39ac8de8fb6@intel.com> (raw)
In-Reply-To: <4fdb6000-ced9-1713-cace-8e7b09c6d586@redhat.com>



On 9/6/20 9:16 AM, Tom Rix wrote:
> On 9/4/20 4:53 PM, Russ Weight wrote:
>> Extend the Intel Security Manager class driver to
>> include an update/status sysfs node that can be polled
>> and read to monitor the progress of an ongoing secure
>> update. Sysfs_notify() is used to signal transitions
>> between different phases of the update process.
>>
>> Signed-off-by: Russ Weight <russell.h.weight@intel.com>
>> Reviewed-by: Wu Hao <hao.wu@intel.com>
>> ---
>>  .../ABI/testing/sysfs-class-ifpga-sec-mgr     | 11 ++++++
>>  drivers/fpga/ifpga-sec-mgr.c                  | 34 ++++++++++++++++---
>>  2 files changed, 41 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-class-ifpga-sec-mgr b/Documentation/ABI/testing/sysfs-class-ifpga-sec-mgr
>> index a476504b7ae9..849ccb2802f8 100644
>> --- a/Documentation/ABI/testing/sysfs-class-ifpga-sec-mgr
>> +++ b/Documentation/ABI/testing/sysfs-class-ifpga-sec-mgr
>> @@ -86,3 +86,14 @@ Description:	Write only. Write the filename of an Intel image
>>  		BMC images, BMC firmware, Static Region images,
>>  		and Root Entry Hashes, and to cancel Code Signing
>>  		Keys (CSK).
>> +
>> +What: 		/sys/class/ifpga_sec_mgr/ifpga_secX/update/status
>> +Date:		Sep 2020
>> +KernelVersion:  5.10
>> +Contact:	Russ Weight <russell.h.weight@intel.com>
>> +Description:	Read-only. Returns a string describing the current
>> +		status of an update. The string will be one of the
>> +		following: idle, read_file, preparing, writing,
> For consistency, read_file -> reading
Yes - I'll make the change.
>> +		programming. Userspace code can poll on this file,
>> +		as it will be signaled by sysfs_notify() on each
>> +		state change.
>> diff --git a/drivers/fpga/ifpga-sec-mgr.c b/drivers/fpga/ifpga-sec-mgr.c
>> index 73173badbe96..5fe3d85e2963 100644
>> --- a/drivers/fpga/ifpga-sec-mgr.c
>> +++ b/drivers/fpga/ifpga-sec-mgr.c
>> @@ -139,6 +139,13 @@ static struct attribute *sec_mgr_security_attrs[] = {
>>  	NULL,
>>  };
>>  
>> +static void update_progress(struct ifpga_sec_mgr *imgr,
>> +			    enum ifpga_sec_prog new_progress)
>> +{
>> +	imgr->progress = new_progress;
>> +	sysfs_notify(&imgr->dev.kobj, "update", "status");
>> +}
>> +
>>  static void ifpga_sec_dev_error(struct ifpga_sec_mgr *imgr,
>>  				enum ifpga_sec_err err_code)
>>  {
>> @@ -149,7 +156,7 @@ static void ifpga_sec_dev_error(struct ifpga_sec_mgr *imgr,
>>  static void progress_complete(struct ifpga_sec_mgr *imgr)
>>  {
>>  	mutex_lock(&imgr->lock);
>> -	imgr->progress = IFPGA_SEC_PROG_IDLE;
>> +	update_progress(imgr, IFPGA_SEC_PROG_IDLE);
>>  	complete_all(&imgr->update_done);
>>  	mutex_unlock(&imgr->lock);
>>  }
>> @@ -177,14 +184,14 @@ static void ifpga_sec_mgr_update(struct work_struct *work)
>>  		goto release_fw_exit;
>>  	}
>>  
>> -	imgr->progress = IFPGA_SEC_PROG_PREPARING;
>> +	update_progress(imgr, IFPGA_SEC_PROG_PREPARING);
>>  	ret = imgr->iops->prepare(imgr);
>>  	if (ret) {
>>  		ifpga_sec_dev_error(imgr, ret);
>>  		goto modput_exit;
>>  	}
>>  
>> -	imgr->progress = IFPGA_SEC_PROG_WRITING;
>> +	update_progress(imgr, IFPGA_SEC_PROG_WRITING);
>>  	size = imgr->remaining_size;
>>  	while (size) {
>>  		blk_size = min_t(u32, size, WRITE_BLOCK_SIZE);
>> @@ -199,7 +206,7 @@ static void ifpga_sec_mgr_update(struct work_struct *work)
>>  		offset += blk_size;
>>  	}
>>  
>> -	imgr->progress = IFPGA_SEC_PROG_PROGRAMMING;
>> +	update_progress(imgr, IFPGA_SEC_PROG_PROGRAMMING);
>>  	ret = imgr->iops->poll_complete(imgr);
>>  	if (ret) {
>>  		ifpga_sec_dev_error(imgr, ret);
>> @@ -251,6 +258,24 @@ static struct attribute_group sec_mgr_security_attr_group = {
>>  	.is_visible = sec_mgr_visible,
>>  };
>>  
>> +static const char * const sec_mgr_prog_str[] = {
>> +	"idle",			/* IFPGA_SEC_PROG_IDLE */
>> +	"read_file",		/* IFPGA_SEC_PROG_READ_FILE */
> "reading"
yes
>> +	"preparing",		/* IFPGA_SEC_PROG_PREPARING */
>> +	"writing",		/* IFPGA_SEC_PROG_WRITING */
>> +	"programming"		/* IFPGA_SEC_PROG_PROGRAMMING */
>> +};
>> +
>> +static ssize_t
>> +status_show(struct device *dev, struct device_attribute *attr, char *buf)
>> +{
>> +	struct ifpga_sec_mgr *imgr = to_sec_mgr(dev);
>> +
>> +	return sprintf(buf, "%s\n", (imgr->progress < IFPGA_SEC_PROG_MAX) ?
>> +		       sec_mgr_prog_str[imgr->progress] : "unknown-status");
> when imgr->progress is unknown, should there be a dev_warn ?
Yes, this is a case that should not happen so it probably warrants something in
the kernel log. I'll add that.
>
> Tom
>
>> +}
>> +static DEVICE_ATTR_RO(status);
>> +
>>  static ssize_t filename_store(struct device *dev, struct device_attribute *attr,
>>  			      const char *buf, size_t count)
>>  {
>> @@ -288,6 +313,7 @@ static DEVICE_ATTR_WO(filename);
>>  
>>  static struct attribute *sec_mgr_update_attrs[] = {
>>  	&dev_attr_filename.attr,
>> +	&dev_attr_status.attr,
>>  	NULL,
>>  };
>>  


  reply	other threads:[~2020-09-22 22:31 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 23:52 [PATCH v1 00/12] Intel FPGA Security Manager Class Driver Russ Weight
2020-09-04 23:52 ` [PATCH v1 01/12] fpga: fpga security manager class driver Russ Weight
2020-09-04 23:57   ` Randy Dunlap
2020-09-05  0:23   ` Moritz Fischer
2020-09-05  0:44     ` Russ Weight
2020-09-05 13:39       ` Wu, Hao
2020-09-05 19:09   ` Tom Rix
     [not found]     ` <ebf251a0-5f13-d1a1-6915-e3c940bb19fe@intel.com>
2020-09-10 21:51       ` Tom Rix
2020-09-10 23:05         ` Russ Weight
2020-09-16 20:16   ` Moritz Fischer
2020-09-30 20:54     ` Russ Weight
2020-10-01  0:31       ` Moritz Fischer
2020-10-01  1:07         ` Russ Weight
2020-10-01 19:07           ` Moritz Fischer
2020-09-04 23:52 ` [PATCH v1 02/12] fpga: create intel max10 bmc security engine Russ Weight
2020-09-05  0:01   ` Randy Dunlap
2020-09-05  0:05     ` Russ Weight
2020-09-05 20:22   ` Tom Rix
2020-09-14 19:07     ` Russ Weight
2020-09-14 20:48       ` Tom Rix
2020-09-14 21:40         ` Russ Weight
2020-09-16 20:33   ` Moritz Fischer
2020-09-30 23:14     ` Russ Weight
2020-09-04 23:52 ` [PATCH v1 03/12] fpga: expose max10 flash update counts in sysfs Russ Weight
2020-09-05 20:39   ` Tom Rix
2020-09-16 18:37     ` Russ Weight
2020-09-04 23:52 ` [PATCH v1 04/12] fpga: expose max10 canceled keys " Russ Weight
2020-09-05 20:52   ` Tom Rix
2020-09-04 23:52 ` [PATCH v1 05/12] fpga: enable secure updates Russ Weight
2020-09-05 22:04   ` Tom Rix
     [not found]     ` <1d90bfb6-417c-55df-9290-991c391158a9@intel.com>
2020-09-20 15:24       ` Tom Rix
2020-09-04 23:52 ` [PATCH v1 06/12] fpga: add max10 secure update functions Russ Weight
2020-09-06 16:10   ` Tom Rix
2020-09-22  1:15     ` Russ Weight
2020-09-08  8:05   ` Lee Jones
2020-09-04 23:53 ` [PATCH v1 07/12] fpga: expose sec-mgr update status Russ Weight
2020-09-06 16:16   ` Tom Rix
2020-09-22 22:31     ` Russ Weight [this message]
2020-09-04 23:53 ` [PATCH v1 08/12] fpga: expose sec-mgr update errors Russ Weight
2020-09-06 16:27   ` Tom Rix
2020-09-22 23:42     ` Russ Weight
2020-09-23 12:52       ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 09/12] fpga: expose sec-mgr update size Russ Weight
2020-09-06 16:39   ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 10/12] fpga: enable sec-mgr update cancel Russ Weight
2020-09-06 17:00   ` Tom Rix
     [not found]     ` <678f8d39-a244-42d0-4c56-91eb859b43f0@intel.com>
2020-09-23 13:02       ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 11/12] fpga: expose hardware error info in sysfs Russ Weight
2020-09-06 17:06   ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 12/12] fpga: add max10 get_hw_errinfo callback func Russ Weight
2020-09-06 17:14   ` Tom Rix
2020-09-24 21:48     ` Russ Weight
2020-09-05 14:13 ` [PATCH v1 00/12] Intel FPGA Security Manager Class Driver Wu, Hao
2020-10-01 20:42   ` Russ Weight
2020-09-05 16:10 ` Tom Rix
2020-09-05 17:16 ` Tom Rix
2020-10-01  0:19   ` Russ Weight

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