From: Stanimir Varbanov <svarbanov@mm-sol.com>
To: Ansuel Smith <ansuelsmth@gmail.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Sham Muthayyan <smuthayy@codeaurora.org>,
Andy Gross <agross@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Andrew Murray <amurray@thegoodpenguin.co.uk>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set tx term offset
Date: Wed, 13 May 2020 14:37:43 +0300 [thread overview]
Message-ID: <3dc89ec6-d550-9402-1a4a-ca0c6f1e1fb9@mm-sol.com> (raw)
In-Reply-To: <20200430220619.3169-10-ansuelsmth@gmail.com>
Hi Ansuel,
On 5/1/20 1:06 AM, Ansuel Smith wrote:
> From: Sham Muthayyan <smuthayy@codeaurora.org>
>
> Add tx term offset support to pcie qcom driver need in some revision of
> the ipq806x SoC.
> Ipq8064 have tx term offset set to 7.
> Ipq8064-v2 revision and ipq8065 have the tx term offset set to 0.
>
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index da8058fd1925..372d2c8508b5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -45,6 +45,9 @@
> #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
>
> #define PCIE20_PARF_PHY_CTRL 0x40
> +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(12, 16)
The mask definition is not correct. Should be GENMASK(20, 16)
> +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
> +
> #define PCIE20_PARF_PHY_REFCLK 0x4C
> #define PHY_REFCLK_SSP_EN BIT(16)
> #define PHY_REFCLK_USE_PAD BIT(12)
> @@ -118,6 +121,7 @@ struct qcom_pcie_resources_2_1_0 {
> u32 tx_swing_full;
> u32 tx_swing_low;
> u32 rx0_eq;
> + u8 phy_tx0_term_offset;
> };
>
> struct qcom_pcie_resources_1_0_0 {
> @@ -318,6 +322,11 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
> if (IS_ERR(res->ext_reset))
> return PTR_ERR(res->ext_reset);
>
> + if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064"))
> + res->phy_tx0_term_offset = 7;
Before your change the phy_tx0_term_offser was 0 for apq8064, but here
you change it to 7, why?
> + else
> + res->phy_tx0_term_offset = 0;
> +
> res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
> return PTR_ERR_OR_ZERO(res->phy_reset);
> }
> @@ -402,6 +411,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> /* enable PCIe clocks and resets */
> qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
>
> + /* set TX termination offset */
> + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL,
> + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
As the mask definition is incorrect you actually clear 12 to 16 bit in
the register where is another PHY parameter. Is that was intentional?
> + PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
> +
> writel(PCS_DEEMPH_TX_DEEMPH_GEN1(res->tx_deemph_gen1) |
> PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(res->tx_deemph_gen2_3p5db) |
> PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(res->tx_deemph_gen2_6db),
> @@ -1485,6 +1499,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
> { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
> + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
> { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
> { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
> { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
>
--
regards,
Stan
next prev parent reply other threads:[~2020-05-13 11:37 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 22:06 [PATCH v3 00/11] Multiple fixes in PCIe qcom driver Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-05-07 17:54 ` Rob Herring
2020-05-08 11:51 ` Stanimir Varbanov
2020-04-30 22:06 ` [PATCH v3 02/11] devicetree: bindings: pci: add missing clks to qcom,pcie Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 03/11] PCI: qcom: change duplicate PCI reset to phy reset Ansuel Smith
2020-05-07 17:57 ` Rob Herring
2020-04-30 22:06 ` [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x Ansuel Smith
2020-05-07 18:00 ` Rob Herring
2020-05-08 7:20 ` Philipp Zabel
2020-04-30 22:06 ` [PATCH v3 05/11] devicetree: bindings: pci: add ext reset to qcom,pcie Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 06/11] PCI: qcom: introduce qcom_clear_and_set_dword Ansuel Smith
2020-05-07 18:07 ` Rob Herring
2020-04-30 22:06 ` [PATCH v3 07/11] PCI: qcom: add support for defining some PARF params Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 08/11] devicetree: bindings: pci: document PARF params bindings Ansuel Smith
2020-05-07 18:10 ` Rob Herring
2020-05-07 19:34 ` R: " ansuelsmth
2020-05-12 15:45 ` Rob Herring
2020-05-13 11:43 ` Stanimir Varbanov
2020-05-13 12:56 ` R: " ansuelsmth
2020-05-20 10:01 ` Stanimir Varbanov
2020-04-30 22:06 ` [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set tx term offset Ansuel Smith
2020-05-07 18:13 ` Rob Herring
2020-05-08 22:00 ` R: " ansuelsmth
2020-05-13 11:37 ` Stanimir Varbanov [this message]
2020-05-13 12:54 ` ansuelsmth
2020-05-13 13:49 ` Stanimir Varbanov
2020-04-30 22:06 ` [PATCH v3 10/11] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie Ansuel Smith
2020-05-07 18:14 ` Rob Herring
2020-04-30 22:06 ` [PATCH v3 11/11] PCI: qcom: add Force GEN1 support Ansuel Smith
2020-05-01 17:07 ` [PATCH v3 00/11] Multiple fixes in PCIe qcom driver Bjorn Helgaas
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