From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D08F4C433EF for ; Fri, 20 May 2022 02:58:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344929AbiETC6z (ORCPT ); Thu, 19 May 2022 22:58:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230028AbiETC6w (ORCPT ); Thu, 19 May 2022 22:58:52 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86D31606FE; Thu, 19 May 2022 19:58:50 -0700 (PDT) X-UUID: b225131989d949c0a19a00dd87d0e9de-20220520 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:e49bcbe8-ceba-4862-bd5d-435c9df4e4b9,OB:0,LO B:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:45 X-CID-INFO: VERSION:1.1.5,REQID:e49bcbe8-ceba-4862-bd5d-435c9df4e4b9,OB:0,LOB: 10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:45 X-CID-META: VersionHash:2a19b09,CLOUDID:59f0f079-5ef6-470b-96c9-bdb8ced32786,C OID:37c94442f15b,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:0,BEC:nil X-UUID: b225131989d949c0a19a00dd87d0e9de-20220520 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 365575824; Fri, 20 May 2022 10:58:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 20 May 2022 10:58:43 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 May 2022 10:58:42 +0800 Message-ID: <3f39777a225fac66f01858262defcc11c6135bb2.camel@mediatek.com> Subject: Re: [PATCH v7 13/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 From: Rex-BC Chen To: "mturquette@baylibre.com" , "sboyd@kernel.org" , "matthias.bgg@gmail.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" CC: "p.zabel@pengutronix.de" , "angelogioacchino.delregno@collabora.com" , Chun-Jie Chen =?UTF-8?Q?=28=E9=99=B3=E6=B5=9A=E6=A1=80=29?= , "wenst@chromium.org" , Runyang Chen =?UTF-8?Q?=28=E9=99=88=E6=B6=A6=E6=B4=8B=29?= , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , Project_Global_Chrome_Upstream_Group Date: Fri, 20 May 2022 10:58:43 +0800 In-Reply-To: <20220519125527.18544-14-rex-bc.chen@mediatek.com> References: <20220519125527.18544-1-rex-bc.chen@mediatek.com> <20220519125527.18544-14-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2022-05-19 at 20:55 +0800, Rex-BC Chen wrote: > To support reset of infra_ao, add the index of infra_ao reset of > thermal/svs/pcei for MT8192 and thermal/svs for MT8195. > > Signed-off-by: Rex-BC Chen > Acked-by: Krzysztof Kozlowski > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++ > include/dt-bindings/reset/mt8195-resets.h | 6 ++++++ > 2 files changed, 14 insertions(+) > > diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt- > bindings/reset/mt8192-resets.h > index 764ca9910fa9..12e2087c90a3 100644 > --- a/include/dt-bindings/reset/mt8192-resets.h > +++ b/include/dt-bindings/reset/mt8192-resets.h > @@ -7,6 +7,7 @@ > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 > #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 > > +/* TOPRGU resets */ > #define MT8192_TOPRGU_MM_SW_RST > 1 > #define MT8192_TOPRGU_MFG_SW_RST 2 > #define MT8192_TOPRGU_VENC_SW_RST 3 > @@ -30,4 +31,11 @@ > /* MMSYS resets */ > #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 > > +/* INFRA resets */ > +#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 > +#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 > +#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 > +#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 > +#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ > diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt- > bindings/reset/mt8195-resets.h > index a26bccc8b957..0b1937f14b36 100644 > --- a/include/dt-bindings/reset/mt8195-resets.h > +++ b/include/dt-bindings/reset/mt8195-resets.h > @@ -7,6 +7,7 @@ > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 > #define _DT_BINDINGS_RESET_CONTROLLER_MT8195 > > +/* TOPRGU resets */ > #define MT8195_TOPRGU_CONN_MCU_SW_RST 0 > #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 > #define MT8195_TOPRGU_APU_SW_RST 2 > @@ -26,4 +27,9 @@ > > #define MT8195_TOPRGU_SW_RST_NUM 16 > > +/* INFRA resets */ > +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0 > +#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1 > +#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2 > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ > -- > 2.18.0 > Hello Stephen, this patch will have conflict with Matthias's commit branch for include/dt-bindings/reset/mt8192-resets.h. It's on linux-next. I have fix it in this version, but I think there will be a merge conflict if you pick my series in this run. https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/include/dt-bindings/reset/mt8192-resets.h?h=next-20220519&id=19c66219e4d5b813ebbd28621cfe9c450659ded7 BRs, Rex