From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88CEFC4332B for ; Fri, 20 Mar 2020 10:05:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C51420754 for ; Fri, 20 Mar 2020 10:05:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584698725; bh=xLCoBe0k1tJ3NSXx1P/PDSVPbSYu5y2TzULMMiyBlTg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=U8Nsf+pDS5rtEWj8tSp+hNZwf2Uhej06qltnbDMGUX+pXQuoJxH7Llj1+6Ys9Cklp Ti1BFqkvgdfsOFzH4rkvB8duAMWtA7Dr+JSpiDG4UgSGWKgO85IV+s4OkApkJc4hw8 hQ/FQv0xpEyp3HfQVViGAU3dnXKn8W0t3n09feP4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727093AbgCTKFY (ORCPT ); Fri, 20 Mar 2020 06:05:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:33696 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726527AbgCTKFY (ORCPT ); Fri, 20 Mar 2020 06:05:24 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0226120739; Fri, 20 Mar 2020 10:05:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584698723; bh=xLCoBe0k1tJ3NSXx1P/PDSVPbSYu5y2TzULMMiyBlTg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=fG3/FshLRVkUpD6f8kWzo2ZRvJ1Hf8TYHFGIVvQTGCajdFE86lnw5LcRvB+oaiwhz LIpRK5YowcZKkauW9vpsoRF0N5qgJXofZdNSufOEynagyl2fv09fg4W9jMxYhRQq8k PDi+QMvsd3CnTUcHcBthjBlrGzlCLFculZqkoH7w= Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1jFEWn-00ECvU-B0; Fri, 20 Mar 2020 10:05:21 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 20 Mar 2020 10:05:21 +0000 From: Marc Zyngier To: Auger Eric Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi , Jason Cooper , Robert Richter , Thomas Gleixner , Zenghui Yu , James Morse , Julien Thierry , Suzuki K Poulose Subject: Re: [PATCH v5 18/23] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers In-Reply-To: <06705d70-0f99-e719-af52-1a5f778562d8@redhat.com> References: <20200304203330.4967-1-maz@kernel.org> <20200304203330.4967-19-maz@kernel.org> <06705d70-0f99-e719-af52-1a5f778562d8@redhat.com> Message-ID: <3f7094ffd77a6615d7179be94dbecc60@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: eric.auger@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, jason@lakedaemon.net, rrichter@marvell.com, tglx@linutronix.de, yuzenghui@huawei.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Eric, On 2020-03-20 08:11, Auger Eric wrote: > Hi Marc, > On 3/4/20 9:33 PM, Marc Zyngier wrote: >> Most of the GICv3 emulation code that deals with SGIs now has to be >> aware of the v4.1 capabilities in order to benefit from it. >> >> Add such support, keyed on the interrupt having the hw flag set and >> being a SGI. >> >> Signed-off-by: Marc Zyngier >> --- >> virt/kvm/arm/vgic/vgic-mmio-v3.c | 15 +++++- >> virt/kvm/arm/vgic/vgic-mmio.c | 88 >> ++++++++++++++++++++++++++++++-- >> 2 files changed, 96 insertions(+), 7 deletions(-) >> [...] >> @@ -113,7 +125,21 @@ void vgic_mmio_write_senable(struct kvm_vcpu >> *vcpu, >> struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); >> >> raw_spin_lock_irqsave(&irq->irq_lock, flags); >> - if (vgic_irq_is_mapped_level(irq)) { >> + if (irq->hw && vgic_irq_is_sgi(irq->intid)) { >> + if (!irq->enabled) { >> + struct irq_data *data; >> + >> + irq->enabled = true; >> + data = &irq_to_desc(irq->host_irq)->irq_data; >> + while (irqd_irq_disabled(data)) >> + enable_irq(irq->host_irq); > could you explain me why the while() is requested? Ah, interesting question: disable_irq() (and its variants) can nest. This means that if you have done two disable_irq(), you must do two enable_irq() to get back to the interrupt being enabled. The locking should ensure that this nesting doesn't happen, but I'm paranoid (see the GICv4.0 doorbell handling). It also makes it easier to reason about the initial state. [...] > Reviewed-by: Eric Auger Thanks! M. -- Jazz is not dead. It just smells funny...