From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43169C07E9B for ; Fri, 9 Jul 2021 07:29:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19E2F611F1 for ; Fri, 9 Jul 2021 07:29:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231192AbhGIHbn (ORCPT ); Fri, 9 Jul 2021 03:31:43 -0400 Received: from mail-0201.mail-europe.com ([51.77.79.158]:57989 "EHLO mail-0201.mail-europe.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230121AbhGIHbm (ORCPT ); Fri, 9 Jul 2021 03:31:42 -0400 Date: Fri, 09 Jul 2021 07:28:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1625815705; bh=RkfvnmLdaWZqZxjDUvmzYCOv0xZV2QzxYSVXkQHzzbM=; h=Date:To:From:Cc:Reply-To:Subject:In-Reply-To:References:From; b=WIEBp5X3N39INqaynv4SEqwjar9wa/XWQet0WZeAlFZ25c9ng3WZ/q0o2y/NV3exc NORKsapydxEGEGLq5saeDxHg5xAuxF/ic2EPr0prdJjWT1h6bW315BdRxKwEKxWTwx ZkM6uaw18g5BZZzw/HvNNDDvMUbCYLoI8SHtLOe0= To: Rob Clark From: Yassine Oudjana Cc: dri-devel@lists.freedesktop.org, Rob Clark , Dmitry Baryshkov , John Stultz , Sean Paul , David Airlie , Daniel Vetter , Bjorn Andersson , Jordan Crouse , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Reply-To: Yassine Oudjana Subject: Re: [PATCH] drm/msm: Fix display fault handling Message-ID: <3pFCrTgsGtxAZ1a2xns0dgqCOz61HZr4foJlLOl1l3I@cp4-web-034.plabs.ch> In-Reply-To: <20210707180113.840741-1-robdclark@gmail.com> References: <20210707180113.840741-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 7 2021 at 21:57:05 +0400, Rob Clark =20 wrote: > From: Rob Clark >=20 > It turns out that when the display is enabled by the bootloader, we=20 > can > get some transient iommu faults from the display. Which doesn't go=20 > over > too well when we install a fault handler that is gpu specific. To=20 > avoid > this, defer installing the fault handler until we get around to=20 > setting > up per-process pgtables (which is adreno_smmu specific). The arm-smmu > fallback error reporting is sufficient for reporting display related > faults (and in fact was all we had prior to=20 > f8f934c180f629bb927a04fd90d) >=20 > Reported-by: Dmitry Baryshkov > Reported-by: Yassine Oudjana > Fixes: 2a574cc05d38 ("drm/msm: Improve the a6xx page fault handler") > Signed-off-by: Rob Clark > Tested-by: John Stultz > --- > drivers/gpu/drm/msm/msm_iommu.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/msm/msm_iommu.c=20 > b/drivers/gpu/drm/msm/msm_iommu.c > index eed2a762e9dd..bcaddbba564d 100644 > --- a/drivers/gpu/drm/msm/msm_iommu.c > +++ b/drivers/gpu/drm/msm/msm_iommu.c > @@ -142,6 +142,9 @@ static const struct iommu_flush_ops null_tlb_ops=20 > =3D { > =09.tlb_add_page =3D msm_iommu_tlb_add_page, > }; >=20 > +static int msm_fault_handler(struct iommu_domain *domain, struct=20 > device *dev, > +=09=09unsigned long iova, int flags, void *arg); > + > struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) > { > =09struct adreno_smmu_priv *adreno_smmu =3D dev_get_drvdata(parent->dev)= ; > @@ -157,6 +160,13 @@ struct msm_mmu=20 > *msm_iommu_pagetable_create(struct msm_mmu *parent) > =09if (!ttbr1_cfg) > =09=09return ERR_PTR(-ENODEV); >=20 > +=09/* > +=09 * Defer setting the fault handler until we have a valid adreno_smmu > +=09 * to avoid accidentially installing a GPU specific fault handler=20 > for > +=09 * the display's iommu > +=09 */ > +=09iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); > + > =09pagetable =3D kzalloc(sizeof(*pagetable), GFP_KERNEL); > =09if (!pagetable) > =09=09return ERR_PTR(-ENOMEM); > @@ -300,7 +310,6 @@ struct msm_mmu *msm_iommu_new(struct device *dev,=20 > struct iommu_domain *domain) >=20 > =09iommu->domain =3D domain; > =09msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); > -=09iommu_set_fault_handler(domain, msm_fault_handler, iommu); >=20 > =09atomic_set(&iommu->pagetables, 0); >=20 > -- > 2.31.1 >=20 Tested-by: Yassine Oudjana