From: Michael Walle <michael@walle.cc>
To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>
Subject: Re: [PATCH 1/4] dt-bindings: clock: document the fsl-flexspi-clk driver
Date: Sun, 01 Nov 2020 20:26:07 +0100 [thread overview]
Message-ID: <4011caa68fe04fcd41f44038bf6b6e5c@walle.cc> (raw)
In-Reply-To: <20201101192053.18644-1-michael@walle.cc>
Hi,
Sorry, I've forgot the cover letter. Next version will have one.
On Layerscape SoCs which feature the FlexSPI controller there is
a single register which can control the divider value. The base
frequency is the platform PLL.
Right now the LS1028A and the LX2160A aren't able to switch the
SCK frequency on the FlexSPI interface. Add a new clock driver
which operate on said register.
-michael
next prev parent reply other threads:[~2020-11-01 19:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-01 19:20 [PATCH 1/4] dt-bindings: clock: document the fsl-flexspi-clk driver Michael Walle
2020-11-01 19:20 ` [PATCH 2/4] clk: fsl-flexspi: new driver Michael Walle
2020-11-01 19:20 ` [PATCH 3/4] arm64: dts: ls1028a: fix FlexSPI clock Michael Walle
2020-11-01 19:20 ` [PATCH 4/4] arm64: dts: lx2160a: " Michael Walle
2020-11-01 19:26 ` Michael Walle [this message]
2020-11-04 22:34 ` [PATCH 1/4] dt-bindings: clock: document the fsl-flexspi-clk driver Rob Herring
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