From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57D97C4338F for ; Mon, 2 Aug 2021 07:43:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33FCC60F9F for ; Mon, 2 Aug 2021 07:43:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232545AbhHBHnh (ORCPT ); Mon, 2 Aug 2021 03:43:37 -0400 Received: from foss.arm.com ([217.140.110.172]:59680 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232435AbhHBHnf (ORCPT ); Mon, 2 Aug 2021 03:43:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69F1B106F; Mon, 2 Aug 2021 00:43:26 -0700 (PDT) Received: from [10.163.66.153] (unknown [10.163.66.153]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 95A293F719; Mon, 2 Aug 2021 00:43:22 -0700 (PDT) Subject: Re: [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com References: <20210728135217.591173-1-suzuki.poulose@arm.com> <20210728135217.591173-8-suzuki.poulose@arm.com> From: Anshuman Khandual Message-ID: <4011d566-1a5b-51a3-dcee-09f60af0a7bb@arm.com> Date: Mon, 2 Aug 2021 13:14:13 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210728135217.591173-8-suzuki.poulose@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/28/21 7:22 PM, Suzuki K Poulose wrote: > Arm Neoverse-N2 and the Cortex-A710 cores are affected > by a CPU erratum where the TRBE will overwrite the trace buffer > in FILL mode. The TRBE doesn't stop (as expected in FILL mode) > when it reaches the limit and wraps to the base to continue > writing upto 3 cache lines. This will overwrite any trace that > was written previously. > > Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum Small nit. Stray 'i' here ^^^^ > (#2119858) to the detection logic. > > This will be used by the TRBE driver in later patches to work > around the issue. The detection has been kept with the core > arm64 errata framework list to make sure : > - We don't duplicate the framework in TRBE driver > - The errata detection is advertised like the rest > of the CPU errata. > > Note that the Kconfig entries will be added after we have added > the work around in the TRBE driver, which depends on the cpucap > from here. > > Cc: Will Deacon > Cc: Mark Rutland > Cc: Anshuman Khandual > Cc: Catalin Marinas > Cc: Mathieu Poirier > Cc: Mike Leach > cc: Leo Yan > Signed-off-by: Suzuki K Poulose > --- > arch/arm64/kernel/cpu_errata.c | 25 +++++++++++++++++++++++++ > arch/arm64/tools/cpucaps | 1 + > 2 files changed, 26 insertions(+) > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index e2c20c036442..ccd757373f36 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -340,6 +340,18 @@ static const struct midr_range erratum_1463225[] = { > }; > #endif > > +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > +static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > +#ifdef CONFIG_ARM64_ERRATUM_2139208 > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2119858 > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > +#endif > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -533,6 +545,19 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, > ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), > }, > +#endif > +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + { > + /* > + * The erratum work around is handled within the TRBE > + * driver and can be applied per-cpu. So, we can allow > + * a late CPU to come online with this erratum. > + */ > + .desc = "ARM erratum 2119858 or 2139208", > + .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > + CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..1ccb92165bd8 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -53,6 +53,7 @@ WORKAROUND_1418040 > WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > +WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_CAVIUM_23154 > WORKAROUND_CAVIUM_27456 > WORKAROUND_CAVIUM_30115 > Reviewed-by: Anshuman Khandual