From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967845AbdAEETD (ORCPT ); Wed, 4 Jan 2017 23:19:03 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:44363 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967778AbdAEESW (ORCPT ); Wed, 4 Jan 2017 23:18:22 -0500 X-AuditID: b6c32a12-f79e16d000006f6e-48-586dc909f408 Subject: Re: [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy binding To: Jaehoon Chung , linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org, krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com, vivek.gautam@codeaurora.org, pankaj.dubey@samsung.com, cpgs@samsung.com From: Alim Akhtar Message-id: <4110cfa2-bbe8-337e-5f2c-13d82cd23713@samsung.com> Date: Thu, 05 Jan 2017 09:46:13 +0530 User-Agent: Mozilla/5.0 (X11; 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> usbdrdphy1 = &usb3_phy1; > }; > + > +Samsung Exynos SoC series PCIe PHY controller > +-------------------------------------------------- > +Required properties: > +- compatible : Should be set to "samsung,exynos5440-pcie-phy" > +- #phy-cells : Must be zero > +- reg : a register used by phy driver. > + - First is for phy register, second is for block register. > +- reg-names : Must be set to "phy" and "block". > + In general PHY uses a "reference clock" to work, if that is true for 5440 also, will you consider adding an (may be) optional clock properties as well? otherwise this binding looks ok to me. > +Example: > + pcie_phy0: pcie-phy@270000 { > + #phy-cells = <0>; > + compatible = "samsung,exynos5440-pcie-phy"; > + reg = <0x270000 0x1000>, <0x271000 0x40>; > + reg-names = "phy", "block"; > + }; >