From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760232AbbJ3XV4 (ORCPT ); Fri, 30 Oct 2015 19:21:56 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:52289 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750834AbbJ3XVx (ORCPT ); Fri, 30 Oct 2015 19:21:53 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Jisheng Zhang , Ray Jui , gnurou@gmail.com, linux@arm.linux.org.uk, sbranden@broadcom.com, swarren@wwwdotorg.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, thierry.reding@gmail.com, bcm-kernel-feedback-list@broadcom.com, tinamdar@apm.com, bhelgaas@google.com Subject: Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles Date: Sat, 31 Oct 2015 00:21:08 +0100 Message-ID: <4140206.u40gNKhatz@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <20151027101820.2d2a1368@xhacker> References: <1445857334-6936-1-git-send-email-jszhang@marvell.com> <562E6056.3040203@broadcom.com> <20151027101820.2d2a1368@xhacker> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:p4yQTGWjkAXaI7AXbWgYxBKdY/nzHO4Hf+SM5pwX1jiUXaFRYsu OqpdYodxRKD0PdU4Zzyz4cDMyX358yn5pXJB/0RBQeXddDZ4M0+0CF0lHrxjSOF8MKfR928 IhCXcYPaiPItvY9E5lbz5aWrzTcWbZDkDrP6W9ZzYnqPIKZHwQOt4FP/QQ/rrbCTmeQyuQx sdn1wvX35/Yko2sVZLrJw== X-UI-Out-Filterresults: notjunk:1;V01:K0:Mo897v6F29c=:iWSZkX/69tO6m4t73TOEBp 9hC1uQp9BTxri0m0JM2NFm3ujcbw9K8Zug/lYiEauOfqk5DrnrOTrlNLJ5+13OIUZmi94Xb+4 /B7+spoy3E0sBcEgqe65uSJk/XJRVd5uBp5sIXfsR0r2KINPOUA+M10b3ysJxKShpT3THwoH9 41dtO5ZLwrNDMPYgTa2P1NMqcY1mV1fqQcIoCuGnRm1TTIdJeQ7cVeregZce2KsqCXw5lOs6u Qn8MftAY+jJp0rcJzDTGAIr2IUo8AElkBbcJr1QUP7T9t/esuncYKG+E67HO3UDwMo2Z2dQ2z uJcoiey/EBESvbYPnTzeOr2bCnU5/VJZS50GvVAR0b7G658Cq1FR+rfbCqeFQDKQPgrEaNgil XBuDfP0Bmx44/l95vlYpEdTr2jqmewlhx+CefCdTdHi9208BmFSK1zgrbeiDebN0K0G6fUwvN IDzKd16V7I0yHHm88+oVFAwlspOjxhqWyPELEJZroN8HQKVEHxZPnJLJGNLoWE6RT5HIYxSpm lLm9f+tgTMUQcm9ogqcscTRHCO0yOrowMBWha/0Sun5L5BtJpdG+D/WwXz85pKgN0MW2QH3ty kDvAofDCxR3JixTzKmfjuV2AEzInZv0wBCsf32q/HmzZ/eN3nNYQVLMAcW7oUwCG9KFpxCKVj cx0hGsOdB8FN8i/qLxvjBvUF4CPMmPhprBsmWbNg40WDQQaYMD/Z1aMqQuYdfUaeYwvKtB7X/ VGsQah0Yq86rmNPA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 27 October 2015 10:18:20 Jisheng Zhang wrote: > On Mon, 26 Oct 2015 10:18:14 -0700 Ray Jui wrote: > > > Hi Jisheng, > > > > On 10/26/2015 4:02 AM, Jisheng Zhang wrote: > > > Inspired by Russell King's patch[1], I found current iproc also has the > > > same issue of "reading 32-bits from the command register, modifying the > > > command register, and then writing it back has the effect of clearing > > > any status bits that were indicating at that time" as pointed out by > > > Russell. This patch fix this issue by using the pci_generic_config_write. > > > > > > [1]http://www.spinics.net/lists/linux-pci/msg44869.html > > > > > > Signed-off-by: Jisheng Zhang > > > --- > > > drivers/pci/host/pcie-iproc.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c > > > index fe2efb1..0c423f2 100644 > > > --- a/drivers/pci/host/pcie-iproc.c > > > +++ b/drivers/pci/host/pcie-iproc.c > > > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, > > > static struct pci_ops iproc_pcie_ops = { > > > .map_bus = iproc_pcie_map_cfg_bus, > > > .read = pci_generic_config_read32, > > > - .write = pci_generic_config_write32, > > > + .write = pci_generic_config_write, > > > }; > > > > > > static void iproc_pcie_reset(struct iproc_pcie *pcie) > > > > > > > I have already confirmed with the ASIC team that the current iProc PCIe > > controller requires 32-bit aligned access into the configuration space > > due to the way how it was integrated into various iProc SoCs including > > NSP, Cygnus, and NS2. > > > > This change will prevent the driver from working properly. > > > > I've informed our ASIC team about this issue and all future iProc based > > SoCs should be able to support 8-bit, 16-bit access and therefore > > pci_generic_config_write/read can be used for those SoCs. > > Thanks for the information, We discussed the same issue when the X-gene PCI host driver was first reviewed, and someone from APM then clarified that it had the same bug. However, I don't know the details about the Tegra implementation, or whether the X-Gene bug has been fixed in a newer version of the parts, so we need to get confirmation from the respective developers before applying any of the patches. If X-gene has been fixed in the meantime, we need to make sure we match on the exact product numbers in the compatible property so we only do it for the newer ones. Arnd