From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752210AbdF3Ras (ORCPT ); Fri, 30 Jun 2017 13:30:48 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:34935 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751322AbdF3Raq (ORCPT ); Fri, 30 Jun 2017 13:30:46 -0400 Subject: Re: [PATCH] net: axienet: add of_phy_connect call for XAE_PHY_TYPE_MII case To: Alvaro Gamez Machado , Anirudha Sarangi , John Linn , Michal Simek , =?UTF-8?Q?S=c3=b6ren_Brinkmann?= , netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20170630092541.27234-1-alvaro.gamez@hazent.com> From: Florian Fainelli Message-ID: <425aed84-a1b6-b8da-5989-3bef5a03ead4@gmail.com> Date: Fri, 30 Jun 2017 10:30:38 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <20170630092541.27234-1-alvaro.gamez@hazent.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/30/2017 02:25 AM, Alvaro Gamez Machado wrote: > This IP core has support for mii connectivity to the phy, so be ready to > connect to it when this is the case. > > Signed-off-by: Alvaro Gamez Machado > --- > drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > index 33c595f4691d..9b3f55449b5e 100644 > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > @@ -935,7 +935,11 @@ static int axienet_open(struct net_device *ndev) > return ret; > > if (lp->phy_node) { > - if (lp->phy_type == XAE_PHY_TYPE_GMII) { > + if (lp->phy_type == XAE_PHY_TYPE_MII) { > + phydev = of_phy_connect(lp->ndev, lp->phy_node, > + axienet_adjust_link, 0, > + PHY_INTERFACE_MODE_MII); > + } else if (lp->phy_type == XAE_PHY_TYPE_GMII) { > phydev = of_phy_connect(lp->ndev, lp->phy_node, > axienet_adjust_link, 0, > PHY_INTERFACE_MODE_GMII); Seems like this could be simplified even further if the values of lp->phy_type directly mapped to those of phy_interface_t. -- Florian