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From: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzysztof.kozlowski+dt@linaro.org" 
	<krzysztof.kozlowski+dt@linaro.org>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will@kernel.org" <will@kernel.org>,
	"gregory.clement@bootlin.com" <gregory.clement@bootlin.com>,
	"sebastian.hesselbarth@gmail.com"
	<sebastian.hesselbarth@gmail.com>,
	"kostap@marvell.com" <kostap@marvell.com>,
	"robert.marko@sartura.hr" <robert.marko@sartura.hr>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles
Date: Thu, 12 May 2022 00:54:52 +0000	[thread overview]
Message-ID: <429ac287-04bd-af78-2deb-06426af53ea4@alliedtelesis.co.nz> (raw)
In-Reply-To: <YnxYtE9dGn6BwF/8@lunn.ch>


On 12/05/22 12:45, Andrew Lunn wrote:
>> Yes there are registers that you can read to identify the specific chip.
>>
>> It still might be useful to have a expected vs actual check as those ID
>> values are determined by pin strapping resistors.
> That i don't get? Can i turn a
>
> * 98DX2538: 24x1G + 2x10G + 2x10G Stack
>
> into a
>
> * 98DX2535: 24x1G + 4x1G Stack
>
> by strapping its pin differently?

I'm not sure it'd actually work properly but yes there are external 
PU/PD resistors that if you fitted differently would at least make the 
ID say that a 98DX2538 is a 98DX2535. The HW docs have these as 
"reserved" pins that must be pulled up/down depending on the specific part.

In reality I suspect that the different serdes arrangements are based on 
what level of screening the silicon passed (similar to how some SoC 
speed grades are distinguished). So you might be able to go down (i.e. 
2538 -> 2535) but probably not up (i.e 2535 -> 2538).

>
>> It could also be used
>> to validate the dts (e.g. port 20 would be invalid on a 98DX3501). But
>> those are considerations for further down the track.
> Yes, that would be up to the switchdev driver to validate the DT based
> on the ID register.
>
>     Andrew

  reply	other threads:[~2022-05-12  0:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 23:09 [PATCH v6 0/3] arm64: mvebu: Support for Marvell 98DX2530 (and variants) Chris Packham
2022-05-10 23:10 ` [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Chris Packham
2022-05-11 16:34   ` Krzysztof Kozlowski
2022-05-12  1:20     ` Chris Packham
2022-05-12  1:51       ` Chris Packham
2022-05-12 14:45         ` Krzysztof Kozlowski
2022-05-12 10:10       ` Krzysztof Kozlowski
2022-05-11 17:02   ` Andrew Lunn
2022-05-11 23:14     ` Chris Packham
2022-05-12  0:27       ` Andrew Lunn
2022-05-12  0:38         ` Chris Packham
2022-05-12  0:45           ` Andrew Lunn
2022-05-12  0:54             ` Chris Packham [this message]
2022-05-10 23:10 ` [PATCH v6 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Chris Packham
2022-05-11 16:38   ` Krzysztof Kozlowski
2022-05-11 23:49     ` Chris Packham
2022-05-12 14:45       ` Krzysztof Kozlowski
2022-05-10 23:10 ` [PATCH v6 3/3] arm64: marvell: enable the 98DX2530 pinctrl driver Chris Packham

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