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Fri, 7 Jun 2019 06:20:14 +0000 (GMT) Subject: Re: [PATCH v4 12/15] drm/bridge: tc358767: Introduce tc_pllupdate_pllen() To: Andrey Smirnov , dri-devel@lists.freedesktop.org Cc: Laurent Pinchart , Archit Taneja , Tomi Valkeinen , Andrey Gusakov , Philipp Zabel , Cory Tusar , Chris Healy , Lucas Stach , linux-kernel@vger.kernel.org From: Andrzej Hajda Message-ID: <45e628a7-6c99-7bd4-4e59-3add4b6c1eb0@samsung.com> Date: Fri, 7 Jun 2019 08:20:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190607044550.13361-13-andrew.smirnov@gmail.com> Content-Transfer-Encoding: 8bit Content-Language: en-US X-Brightmail-Tracker: H4sIAAAAAAAAA02SW0gUYRTH+2ZmZ2at1XG19mBitV3oqpaRA5Vl9DAPPhj1YCXklpNZutqO WlaQrV221bwi4qppliQlaN5KjSgFp8hbqKGBF0rxUragbWrkmuMo+fY7/3POd/5/+Ghc3aZw o8P1MbxBr4vQkg5ETdNM66712J9g7+nfTmyi6SBrbEhQsEbTuIKd7mwk2HevRYzttFlJdiC/ B2Pvpz+h2I66PJLt7XtPsGUFX8jDK7mOlAcYN5A1h3G1ll6KyzXlKLj+JBHjUme9ObH7JcZN VnhwrVktWKDylMOBUD4iPI43ePmFOFwobc6nou3uV+vtmxNQpcaMlDQwe2GuvYgwIwdazZQg GE4fweXiF4L2qdrFziSCvJ9WfGklo7NuceopgtRRMyUX4whGut9S0pQLcwKMdbYFdmUCYcJY S0qMMzYMOvqUEpPMNpit7JnXaVrF+MFdq6MkE8wmeFhSs3BsNRME/U3lColVjDN8yBkkJFYy h8Bcn0TIT66DxOpcXGYNfBkswCQ/wIxSYG0bRLLrozCTMkbK7AJjYhUlszt8zEwmZL4J/SW3 cXnZhKC6vHYx8n5oFD8pJKP4vOmyOi9Z9gd7YSslycA4Qve4s+zBETJqsnFZVoHprlqe3gD9 LdWLD2qguN1GpiGtZVkyy7I0lmVpLP/vFiLiGdLwsUJkGC/46PkrnoIuUojVh3mei4qsQPPf 7KNdtL1Cb/6ebUAMjbSrVBw1E6xW6OKE+MgGBDSudVXFtU8Hq1WhuvhrvCHqjCE2ghca0Fqa 0GpU11cMnFYzYboY/hLPR/OGpS5GK90SkKFPuUe88nmsqmn10GWXroEi+8nSonszG1948clH XNJTyR2Png2dOvkdvt3yKJ9q/bElwPw4JtPoxxZTTmm33xPDxRlcqXI4b414x3PrDddCn5Dt qqB9XfTOQn3z81Dh2PHmF9qJ7K8X05JX5WbOnS9ZmyBm2qx7oir8fX3zA8qqtYRwQbd7O24Q dP8AO2pLOWIDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIIsWRmVeSWpSXmKPExsVy+t/xe7ryTL9iDK4tE7Jo7rC1aDrUwGrR 1PGW1eLHlcMsFgf3HGeyuPL1PZvFg7k3mSw6Jy5ht7i8aw6bxd17J1gs1s+/xebA7XG5r5fJ 48HU/0weO2fdZfeY3TGT1eN+93Emj/6/Bh7Hb2xn8vi8Sc7j3NSzTAGcUXo2RfmlJakKGfnF JbZK0YYWRnqGlhZ6RiaWeobG5rFWRqZK+nY2Kak5mWWpRfp2CXoZa87MZS/4J1Ox+59qA+Nm 8S5GTg4JAROJSVd2MXcxcnEICSxllJh5+AAjREJcYvf8t8wQtrDEn2tdbBBFrxkl7vXuZwFJ CAuESDTt+soOYosI+El0zTvA1MXIwcEs8J1J4iUfRP0xRom+71fA6tkENCX+br7JBlLDK2An 0faeDyTMIqAiMW/FNrBdogIREmferwAr5xUQlDg58wmYzSlgL9G1uxvMZhZQl/gz7xIzhC0v 0bx1NpQtLnHryXymCYxCs5C0z0LSMgtJyywkLQsYWVYxiqSWFuem5xYb6hUn5haX5qXrJefn bmIERu+2Yz8372C8tDH4EKMAB6MSD68Dw88YIdbEsuLK3EOMEhzMSiK8ZRd+xAjxpiRWVqUW 5ccXleakFh9iNAV6biKzlGhyPjCx5JXEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0t SC2C6WPi4JRqYOyZkb5GcYriZVaO+t2Z7M92eXwTFc1J3n/swcKepdv563+1m/5c0hGwskde olxke7/JxmfrhMsSjZSTjGq5gpvCXZeG8/9Vd/H4Gzr9b0Bua6vUx6hJeiU56qkLbz4LOpbh KrZqxhzGm/H7Zl/83N6Q37v7xdQ9RzvPqDm/uKg3dWHDptSZL5RYijMSDbWYi4oTAVF/Lu70 AgAA X-CMS-MailID: 20190607062015eucas1p2cc1e99f263d505335ece18465b09fc80 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20190607044647epcas1p4293a910d9ceea202cff1473c5cfe93b6 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190607044647epcas1p4293a910d9ceea202cff1473c5cfe93b6 References: <20190607044550.13361-1-andrew.smirnov@gmail.com> <20190607044550.13361-13-andrew.smirnov@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07.06.2019 06:45, Andrey Smirnov wrote: > tc_wait_pll_lock() is always called as a follow-up for updating > PLLUPDATE and PLLEN bit of a given PLL control register. To simplify > things, merge the two operation into a single helper function > tc_pllupdate_pllen() and convert the rest of the code to use it. No > functional change intended. > > Signed-off-by: Andrey Smirnov > Reviewed-by: Laurent Pinchart I guess tc_pllupdate would be OK as well, but shorter. Anyway: Reviewed-by: Andrzej Hajda  -- Regards Andrzej > Cc: Archit Taneja > Cc: Andrzej Hajda > Cc: Laurent Pinchart > Cc: Tomi Valkeinen > Cc: Andrey Gusakov > Cc: Philipp Zabel > Cc: Cory Tusar > Cc: Chris Healy > Cc: Lucas Stach > Cc: dri-devel@lists.freedesktop.org > Cc: linux-kernel@vger.kernel.org > --- > drivers/gpu/drm/bridge/tc358767.c | 30 ++++++++++++++---------------- > 1 file changed, 14 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c > index ac55b59249e3..c994c72eb330 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -443,10 +443,18 @@ static u32 tc_srcctrl(struct tc_data *tc) > return reg; > } > > -static void tc_wait_pll_lock(struct tc_data *tc) > +static int tc_pllupdate_pllen(struct tc_data *tc, unsigned int pllctrl) > { > + int ret; > + > + ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); > + if (ret) > + return ret; > + > /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ > usleep_range(3000, 6000); > + > + return 0; > } > > static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) > @@ -546,13 +554,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) > return ret; > > /* Force PLL parameter update and disable bypass */ > - ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLUPDATE | PLLEN); > - if (ret) > - return ret; > - > - tc_wait_pll_lock(tc); > - > - return 0; > + return tc_pllupdate_pllen(tc, PXL_PLLCTRL); > } > > static int tc_pxl_pll_dis(struct tc_data *tc) > @@ -626,15 +628,13 @@ static int tc_aux_link_setup(struct tc_data *tc) > * Initially PLLs are in bypass. Force PLL parameter update, > * disable PLL bypass, enable PLL > */ > - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); > + ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL); > if (ret) > goto err; > - tc_wait_pll_lock(tc); > > - ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); > + ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL); > if (ret) > goto err; > - tc_wait_pll_lock(tc); > > ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); > if (ret == -ETIMEDOUT) { > @@ -914,15 +914,13 @@ static int tc_main_link_enable(struct tc_data *tc) > return ret; > > /* PLL setup */ > - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); > + ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL); > if (ret) > return ret; > - tc_wait_pll_lock(tc); > > - ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); > + ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL); > if (ret) > return ret; > - tc_wait_pll_lock(tc); > > /* Reset/Enable Main Links */ > dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;