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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id f11-20020a05651c02cb00b00253e1fca85asm318558ljo.85.2022.05.21.08.12.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 May 2022 08:12:56 -0700 (PDT) Message-ID: <45fea4a1-387f-9684-a90b-58b695b54172@linaro.org> Date: Sat, 21 May 2022 17:12:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v5 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Content-Language: en-US To: Tanmay Shah , bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, michal.simek@xilinx.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220518194426.3784095-1-tanmay.shah@xilinx.com> <20220518194426.3784095-2-tanmay.shah@xilinx.com> From: Krzysztof Kozlowski In-Reply-To: <20220518194426.3784095-2-tanmay.shah@xilinx.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/05/2022 21:44, Tanmay Shah wrote: > +description: | > + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for > + real-time processing based on the Cortex-R5F processor core from ARM. > + The Cortex-R5F processor implements the Arm v7-R architecture and includes a > + floating-point unit that implements the Arm VFPv3 instruction set. > + > +properties: > + compatible: > + const: xlnx,zynqmp-r5fss > + > + xlnx,cluster-mode: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1, 2] > + description: | > + The RPU MPCore can operate in split mode(Dual-processor performance), Safety > + lock-step mode(Both RPU cores execute the same code in lock-step, > + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while > + core 1 runs normally). The processor does not support dynamic configuration. > + Switching between modes is only permitted immediately after a processor reset. > + If set to 1 then lockstep mode and if 0 then split mode. > + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. > + > +patternProperties: > + "^r5f-[a-f0-9]+$": > + type: object > + description: | > + The RPU is located in the Low Power Domain of the Processor Subsystem. > + Each processor includes separate L1 instruction and data caches and > + tightly coupled memories (TCM). System memory is cacheable, but the TCM > + memory space is non-cacheable. > + > + Each RPU contains one 64KB memory and two 32KB memories that > + are accessed via the TCM A and B port interfaces, for a total of 128KB > + per processor. In lock-step mode, the processor has access to 256KB of > + TCM memory. > + > + properties: > + compatible: > + const: xlnx,zynqmp-r5f > + > + power-domains: > + description: RPU core PM domain specifier > + maxItems: 1 > + > + mboxes: > + items: > + - description: mailbox channel to send data to RPU > + - description: mailbox channel to receive data from RPU > + minItems: 1 > + > + mbox-names: > + items: > + - const: tx > + - const: rx > + minItems: 1 > + > + sram: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + minItems: 1 maxItems instead > + description: | > + phandles to one or more reserved on-chip SRAM regions. Other than TCM, > + the RPU can execute instructions and access data from, the OCM memory, > + the main DDR memory, and other system memories. > + > + The regions should be defined as child nodes of the respective SRAM > + node, and should be defined as per the generic bindings in, > + Documentation/devicetree/bindings/sram/sram.yaml > + > + memory-region: > + description: | > + List of phandles to the reserved memory regions associated with the > + remoteproc device. This is variable and describes the memories shared with > + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg > + vrings, ...). This reserved memory region will be allocated on DDR memory. > + minItems: 1 > + items: > + - description: region used for RPU firmware image section > + - description: vdev buffer > + - description: vring0 > + - description: vring1 > + additionalItems: true How did this one appear here? It does not look correct, so why do you need it? > + > + required: > + - compatible > + - power-domains > + > + unevaluatedProperties: false > + > +required: > + - compatible > +\ Best regards, Krzysztof