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bh=mQeGFHveTHebaelml1aHZBuXXsokPzTEQ06fsvkfyC8=; b=UtG9lP5VFvuhqPQlki71V59Dat9iXa4GUPWtLR/uLFhcBeUSKCHuOBucVEGbmhiKX2 DJ+1ptOYkALXkTd5TXYqXC+KX9q9hJZx+i8PPQsuEo2K1bHvxCr1sQ5f3OPdz/muZFpG I67GBz8OgQAz/W7098W5C5b+g4k/lXuzTxuUFKQEVcURdt1kCrRLHa5GMKW6+oR/Gfam dkMWXH5DSliuC7oR58mRkb8X8kZ59FTurf4h9JZsccW1TULFnTzXxG6dwdikx2eHRqcN +BsW2zs+jhI/U/X6ojFJ7mfD72SWFtBCpEfI78BXLlZSGTV73M3+krK2F6gFg6b5xKWJ kPzw== X-Gm-Message-State: APjAAAVZo7bVaoTWJmeXcxI3ixraSd8rYgsOvHZ+qxt9578/pnXazwg7 uSzPMEAa8lwKRzvDcduRtU8= X-Google-Smtp-Source: APXvYqzllpl/S6ftD0ojhliYQ7BNkmhWRJWd5RuYBGE6oCjcmoOKKhxaOFNhgTHHtlDgNmIedTuegw== X-Received: by 2002:a62:7a11:: with SMTP id v17mr4919968pfc.191.1576087937559; Wed, 11 Dec 2019 10:12:17 -0800 (PST) Received: from [10.69.78.90] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id t11sm3344493pjf.30.2019.12.11.10.12.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 10:12:16 -0800 (PST) Subject: Re: [PATCH 2/2] reset: Add Broadcom STB RESCAL reset controller To: Philipp Zabel , linux-kernel@vger.kernel.org Cc: Jim Quinlan , Jim Quinlan , Rob Herring , Mark Rutland , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" References: <20191210195903.24127-1-f.fainelli@gmail.com> <20191210195903.24127-3-f.fainelli@gmail.com> <89d2d00058e34e7571fc0f50ce487cf54414cd49.camel@pengutronix.de> From: Florian Fainelli Autocrypt: addr=f.fainelli@gmail.com; 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WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <89d2d00058e34e7571fc0f50ce487cf54414cd49.camel@pengutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/11/2019 1:48 AM, Philipp Zabel wrote: >> +#define BRCM_RESCAL_START 0 >> +#define BRCM_RESCAL_START_BIT BIT(0) >> +#define BRCM_RESCAL_CTRL 4 >> +#define BRCM_RESCAL_STATUS 8 >> +#define BRCM_RESCAL_STATUS_BIT BIT(0) > > Is there any reason the start bit is indented but the status bit is not? This is a convention we have tried to adopt to denote the definition from a register word address/offset versus the definition for bits within that register word. > >> + >> +struct brcm_rescal_reset { >> + void __iomem *base; >> + struct device *dev; >> + struct reset_controller_dev rcdev; >> +}; >> + >> +static int brcm_rescal_reset_assert(struct reset_controller_dev *rcdev, >> + unsigned long id) >> +{ >> + return 0; >> +} > > Please do not implement the assert operation if it doesn't cause a reset > line to be asserted afterwards. > The reset core will return 0 from reset_control_assert() for shared > reset controls if .assert is not implemented. OK, will drop it. > >> + >> +static int brcm_rescal_reset_deassert(struct reset_controller_dev *rcdev, >> + unsigned long id) >> +{ >> + struct brcm_rescal_reset *data = >> + container_of(rcdev, struct brcm_rescal_reset, rcdev); >> + void __iomem *base = data->base; >> + const int NUM_RETRIES = 10; >> + u32 reg; >> + int i; >> + >> + reg = readl(base + BRCM_RESCAL_START); >> + writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); >> + reg = readl(base + BRCM_RESCAL_START); > > Are there any other fields beside the START_BIT in this register? This is the only bit actually. > >> + if (!(reg & BRCM_RESCAL_START_BIT)) { >> + dev_err(data->dev, "failed to start sata/pcie rescal\n"); >> + return -EIO; >> + } >> + >> + reg = readl(base + BRCM_RESCAL_STATUS); >> + for (i = NUM_RETRIES; i >= 0 && !(reg & BRCM_RESCAL_STATUS_BIT); i--) { >> + udelay(100); >> + reg = readl(base + BRCM_RESCAL_STATUS); >> + } > > This timeout loop should be replaced by a single readl_poll_timeout(). > At 100 µs waits per iteration this could use the sleeping variant. OK, will do. > >> + if (!(reg & BRCM_RESCAL_STATUS_BIT)) { >> + dev_err(data->dev, "timedout on sata/pcie rescal\n"); >> + return -ETIMEDOUT; >> + } >> + >> + reg = readl(base + BRCM_RESCAL_START); >> + writel(reg ^ BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); > > Please use &= ~BRCM_RESCAL_START_BIT instead. > I think the idea was to avoid unconditionally clearing it, but based on the documentation, I don't see this being harmful, Jim? >> + reg = readl(base + BRCM_RESCAL_START); >> + dev_dbg(data->dev, "sata/pcie rescal success\n"); >> + >> + return 0; >> +} > > This whole function looks a lot like it doesn't just deassert a reset > line, but actually issues a complete reset procedure of some kind. Do > you have some insight on what actually happens in the hardware when the > start bit is triggered? I suspect this should be implemented with the > .reset operation. This hardware block is controlling the reset and calibration process of the SATA/PCIe combo PHY analog front end, but is not technically part of the PCIe or SATA PHY proper, it stands on its own, both functionally and from a register space perspective. The motivation for modelling this as a reset controller is that it does a reset (and a calibration) and this is a shared reset line among 2/3 instances of another block. If you think we should model this differently, please let us know. -- Florian