From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88F1AC3279B for ; Wed, 4 Jul 2018 15:16:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 436AC22526 for ; Wed, 4 Jul 2018 15:16:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 436AC22526 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753147AbeGDPPS (ORCPT ); Wed, 4 Jul 2018 11:15:18 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39158 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753034AbeGDPPQ (ORCPT ); Wed, 4 Jul 2018 11:15:16 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2F1218A; Wed, 4 Jul 2018 08:15:15 -0700 (PDT) Received: from [192.168.67.35] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D11F33F5AD; Wed, 4 Jul 2018 08:15:13 -0700 (PDT) Subject: Re: [linux-sunxi] Re: [PATCH 0/2] Allwinner A64 timer workaround To: Marc Zyngier Cc: Thomas Gleixner , Daniel Lezcano , Samuel Holland , Maxime Ripard , Chen-Yu Tsai , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Mark Rutland References: <20180511022751.9096-1-samuel@sholland.org> <2c16d5ab-38f7-8f3e-875c-19e8032f440a@arm.com> <5283f98e-6443-db7a-fe51-6379ed19002c@arm.com> <24b78819-5e3f-431f-3987-f7409742ef07@linaro.org> <1d75c538-9166-5eec-a08c-b168f9770bd1@arm.com> <1a36f63c-0259-bdcd-bb96-d5230c2564ea@arm.com> <55fc9e48-6329-df75-3a12-60cc42d91a31@arm.com> <861scjyrio.wl-marc.zyngier@arm.com> From: Andre Przywara Openpgp: preference=signencrypt Autocrypt: addr=andre.przywara@arm.com; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <861scjyrio.wl-marc.zyngier@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 04/07/18 16:01, Marc Zyngier wrote: > On Wed, 04 Jul 2018 15:44:36 +0100, > Andre Przywara wrote: >> >> Hi, >> >> On 04/07/18 15:31, Thomas Gleixner wrote: >>> On Wed, 4 Jul 2018, Andre Przywara wrote: >>>> On 04/07/18 11:00, Thomas Gleixner wrote: >>>>> On Wed, 4 Jul 2018, Marc Zyngier wrote: >>>>>> On 04/07/18 09:23, Daniel Lezcano wrote: >>>>>>> >>>>>>> If the patches fix a bug which already exist, it makes sense to >>>>>>> propagated the fix back to the stable versions. >>>>>> >>>>>> That's your call, but I'm not supportive of that decision, specially as >>>>>> we have information from the person developing the workaround that this >>>>>> doesn't fully address the issue. >>>>> >>>>> The patches should not be applied at all. Simply because they don't fix the >>>>> issue completely. >>>>> >>>>> From a quick glance at various links and information about this, this very >>>>> much smells like the FSL_ERRATUM_A008585. >>>>> Has that been tried? It looks way more robust than the magic 11 bit >>>>> crystal ball logic. >>>> >>>> The Freescale erratum is similar, but not identical [1]. >>>> It seems like the A64 is less variable, so we can use a cheaper >>>> workaround, which gets away with normally just one sysreg read. But then >>>> again the newer error reports may actually suggest otherwise ... >>>> >>>> And as it currently stands, the Freescale erratum has the drawback of >>>> relying on the CPU running much faster than the timer. The A64 can run >>>> at 24 MHz (for power savings, or possibly during DVFS transitions), >>>> which is the timer frequency. So subsequent counter reads will never >>>> return the same value and the workaround times out. >>> >>> If that's the case then you need to find a different functional timer for >>> time keeping. Having an erratic behaving timer for time keeping is not an >>> option at all. >> >> That's not an option on arm64. There are other usable time sources in >> the SoC, but the arch timer is somewhat mandatory for all practical >> purposes on arm64. We rely on it in some many places that it's not >> feasible to run without it. That's why we call it "architected" timer >> after all ;-) >> But I am quite confident that we can find a correct workaround. Maybe >> it's really the TVAL (the downcounter) write which is the culprit here, >> since the hardware actually writes "now() + TVAL" into the CVAL >> (upcounter) register. This internal counter access may be flawed as well. > > You got it backward: CVAL is not a counter at all. It is a > Comparator. And TVAL has an implicit read from the counter, as it is > defined as "CVAL - CNT" (i.e. the number of ticks until the timer > expires). Yes, that's what I meant actually, sorry for the lousy wording. What I am actually more concerned about than reading (do we actually read TVAL?), is writing TVAL. The original BSP errata hack hints at this being a problem: https://github.com/longsleep/linux-pine64/blob/5b10a45ae8b0/drivers/clocksource/arm_arch_timer.c#L231-L244 > So it might be worth trying to handle TVAL entirely in SW. > > But this relies on being able to read the timer and get a number of > correct values out of it. One possibility would be to sacrifice > precision and always ignore some of the bottom bits, but this is > always going to suck terribly. > > The alternative is burn that thing, and pretend it never existed. Yes, that crossed my mind multiple times. Cheers, Andre.