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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id f19-20020a19ae13000000b0047255d211b4sm799894lfc.227.2022.05.14.13.28.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 May 2022 13:28:13 -0700 (PDT) Message-ID: <4714c388-47ec-776a-7a50-362b258ffc25@linaro.org> Date: Sat, 14 May 2022 22:28:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v3 1/2] dt-bindings: gpio: gpio-mvebu: convert txt binding to YAML Content-Language: en-US To: Chris Packham , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "linus.walleij@linaro.org" , "brgl@bgdev.pl" , "thierry.reding@gmail.com" , "u.kleine-koenig@pengutronix.de" , "lee.jones@linaro.org" , "andrew@lunn.ch" , Vadym Kochan , "enachman@marvell.com" Cc: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-pwm@vger.kernel.org" References: <20220512094125.3748197-1-chris.packham@alliedtelesis.co.nz> <32aab734-5890-99b2-09c9-8ec7418c7649@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/05/2022 04:20, Chris Packham wrote: > >>> + >>> +allOf: >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: marvell,armada-8k-gpio >>> + then: >>> + required: >>> + - offset >>> + else: >>> + required: >>> + - reg >> one blank line please >> >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: marvell,armadaxp-gpio >> Original bindings are saying that second reg is optional for >> marvell,armada-370-gpio. What about other cases, e.g. mv78200-gpio? Is >> it also allowed (and optional) there? > This is where things get interesting. The armadaxp (and only the > armadaxp) requires a second register value for some per-cpu registers. > All of the other SoCs can have an optional 2nd register value if they > want to use the PWM function. I guess that implies that the armadaxp > can't do PWM. >>> + then: >>> + properties: >>> + reg: >>> + minItems: 2 >> Then you also should require two reg-names. > > Simple enough to add. But currently we've said that the reg-names are > "gpio" and "pwm" but on the armadaxp the 2nd one is not "pwm" but > something else ("per-cpu" perhaps?) In such case they would be failing with current bindings, because they expect "pwm" as second name, right? > > On the other hand this is all completely moot because the > armada-xp-mv78*.dtsi actually use the "marvell,armada-370-gpio" > compatible so this appears to be documenting something that is no longer > used. Indeed it appears that the armadaxp specific usage was remove in > 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on Armada XP"). > > So perhaps the best course of action is to drop marvell,armadaxp-gpio > from the new binding (noting that we've done so in the commit message). That's fine, maybe in a separate patch (2nd one)? Best regards, Krzysztof