From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB7EDC2D0BF for ; Thu, 5 Dec 2019 10:04:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8776124652 for ; Thu, 5 Dec 2019 10:04:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PAZrJdzh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729275AbfLEKEJ (ORCPT ); Thu, 5 Dec 2019 05:04:09 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54290 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726239AbfLEKEJ (ORCPT ); Thu, 5 Dec 2019 05:04:09 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB5A3skv115735; Thu, 5 Dec 2019 04:03:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575540234; bh=KVdOg686NGTO/lSscHFY4DTCJ8U0Ya2tIRngEQ14Ijs=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=PAZrJdzhxj8TcFMU2LbHzqPQTAquU25WJVwbJvjcrp6rS5q5D/6lmMRqEBxNPw57T UxmxubBtKczv0+AQm6pY4B/+5ha9Iv9OeYoalQ5xkmp+2mCt0Ty1Pnjd2oaMXRAJvP KW2CUwf3L8wshbdRIPai6L6w3KYI85I7RdxlrIdk= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB5A3rtd019638 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Dec 2019 04:03:54 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 5 Dec 2019 04:03:53 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 5 Dec 2019 04:03:53 -0600 Received: from [10.24.69.159] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB5A3noL030226; Thu, 5 Dec 2019 04:03:49 -0600 Subject: Re: [PATCH 1/4] PCI: dwc: Add new feature to skip core initialization To: Vidya Sagar , , , , , , CC: , , , , , , References: <20191113090851.26345-1-vidyas@nvidia.com> <20191113090851.26345-2-vidyas@nvidia.com> From: Kishon Vijay Abraham I Message-ID: <47c801ab-ddec-d436-1f0d-1dd0c4980869@ti.com> Date: Thu, 5 Dec 2019 15:34:59 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191113090851.26345-2-vidyas@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/11/19 2:38 pm, Vidya Sagar wrote: > Add a new feature 'skip_core_init' that can be set by platform drivers > of devices that do not have their core registers available until reference > clock from host is available (Ex:- Tegra194) to indicate DesignWare > endpoint mode sub-system to not perform core registers initialization. > Existing dw_pcie_ep_init() is refactored and all the code that touches > registers is extracted to form a new API dw_pcie_ep_init_complete() that > can be called later by platform drivers setting 'skip_core_init' to '1'. No. pci_epc_features should only use constant values. This is used by function drivers to know the controller capabilities. Thanks Kishon > > Signed-off-by: Vidya Sagar > --- > .../pci/controller/dwc/pcie-designware-ep.c | 72 +++++++++++-------- > drivers/pci/controller/dwc/pcie-designware.h | 6 ++ > include/linux/pci-epc.h | 1 + > 3 files changed, 51 insertions(+), 28 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 3dd2e2697294..06f4379be8a3 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -492,19 +492,53 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) > return 0; > } > > -int dw_pcie_ep_init(struct dw_pcie_ep *ep) > +int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) > { > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + unsigned int offset; > + unsigned int nbars; > + u8 hdr_type; > + u32 reg; > int i; > + > + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); > + if (hdr_type != PCI_HEADER_TYPE_NORMAL) { > + dev_err(pci->dev, > + "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", > + hdr_type); > + return -EIO; > + } > + > + ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); > + > + ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); > + > + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); > + if (offset) { > + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); > + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> > + PCI_REBAR_CTRL_NBAR_SHIFT; > + > + dw_pcie_dbi_ro_wr_en(pci); > + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) > + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); > + dw_pcie_dbi_ro_wr_dis(pci); > + } > + > + dw_pcie_setup(pci); > + > + return 0; > +} > + > +int dw_pcie_ep_init(struct dw_pcie_ep *ep) > +{ > int ret; > - u32 reg; > void *addr; > - u8 hdr_type; > - unsigned int nbars; > - unsigned int offset; > struct pci_epc *epc; > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > struct device *dev = pci->dev; > struct device_node *np = dev->of_node; > + const struct pci_epc_features *epc_features; > > if (!pci->dbi_base || !pci->dbi_base2) { > dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); > @@ -563,13 +597,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > if (ep->ops->ep_init) > ep->ops->ep_init(ep); > > - hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); > - if (hdr_type != PCI_HEADER_TYPE_NORMAL) { > - dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", > - hdr_type); > - return -EIO; > - } > - > ret = of_property_read_u8(np, "max-functions", &epc->max_functions); > if (ret < 0) > epc->max_functions = 1; > @@ -587,23 +614,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); > return -ENOMEM; > } > - ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); > > - ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); > - > - offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); > - if (offset) { > - reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); > - nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> > - PCI_REBAR_CTRL_NBAR_SHIFT; > - > - dw_pcie_dbi_ro_wr_en(pci); > - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) > - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); > - dw_pcie_dbi_ro_wr_dis(pci); > + if (ep->ops->get_features) { > + epc_features = ep->ops->get_features(ep); > + if (epc_features->skip_core_init) > + return 0; > } > > - dw_pcie_setup(pci); > - > - return 0; > + return dw_pcie_ep_init_complete(ep); > } > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 5accdd6bc388..340783e9032e 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -399,6 +399,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp) > #ifdef CONFIG_PCIE_DW_EP > void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); > int dw_pcie_ep_init(struct dw_pcie_ep *ep); > +int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); > void dw_pcie_ep_exit(struct dw_pcie_ep *ep); > int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); > int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > @@ -416,6 +417,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) > return 0; > } > > +static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) > +{ > + return 0; > +} > + > static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > { > } > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > index 36644ccd32ac..241e6a6f39fb 100644 > --- a/include/linux/pci-epc.h > +++ b/include/linux/pci-epc.h > @@ -121,6 +121,7 @@ struct pci_epc_features { > u8 bar_fixed_64bit; > u64 bar_fixed_size[PCI_STD_NUM_BARS]; > size_t align; > + bool skip_core_init; > }; > > #define to_pci_epc(device) container_of((device), struct pci_epc, dev) >