From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC014C433DF for ; Mon, 12 Oct 2020 07:25:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 865DE2087D for ; Mon, 12 Oct 2020 07:25:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602487530; bh=J36sJhtxzl7UwDAHdCIhtRxDUhNjAfyMJ6sQVGj2UnE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=evqbSdzRcnwOlK7QokHe+YlkLNXu3ih6lZgMp5YQ3s9utaPS0ykTE90DUkHoIdTQx kZuMaFjjnF8uyAsvJinmZzbJsJHI4hWBuTRFQBik+r1YWSPHIdB08GCxzeUvN/8nsi /IrAojZ3B9502cPWeTmw88cdaJRtzmo7gKc17vb4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727376AbgJLHZ3 (ORCPT ); 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Mon, 12 Oct 2020 08:25:26 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 12 Oct 2020 08:25:26 +0100 From: Marc Zyngier To: l00484210 Cc: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, fanhenglong@huawei.com, wanghaibin.wang@huawei.com, tangnianyao@huawei.com, jiangyifei@huawei.com, dengkai1@huawei.com, zhang.zhanghailiang@huawei.com, victor.zhangxiaofeng@huawei.com Subject: Re: [PATCH] arm64: KVM: marking pages as XN in Stage-2 does not care about CTR_EL0.DIC In-Reply-To: <20201012010852.15932-1-limingwang@huawei.com> References: <20201012010852.15932-1-limingwang@huawei.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <47f80f46b9bac66846871b2db32a3f92@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: limingwang@huawei.com, catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, fanhenglong@huawei.com, wanghaibin.wang@huawei.com, tangnianyao@huawei.com, jiangyifei@huawei.com, dengkai1@huawei.com, zhang.zhanghailiang@huawei.com, victor.zhangxiaofeng@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Li, On 2020-10-12 02:08, l00484210 wrote: > From: MingWang Li > > When testing the ARMv8.2-TTS2UXN feature, setting bits of XN is > unavailable. > Because the control bit CTR_EL0.DIC is set by default on system. > > But when CTR_EL0.DIC is set, software does not need to flush icache > actively, > instead of clearing XN bits.The patch, the commit id of which > is 6ae4b6e0578886eb36cedbf99f04031d93f9e315, has implemented the > function > of CTR_EL0.DIC. > > Signed-off-by: MingWang Li > Signed-off-by: Henglong Fan > --- > arch/arm64/include/asm/pgtable-prot.h | 12 +----------- > 1 file changed, 1 insertion(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/pgtable-prot.h > b/arch/arm64/include/asm/pgtable-prot.h > index 4d867c6446c4..5feb94882bf7 100644 > --- a/arch/arm64/include/asm/pgtable-prot.h > +++ b/arch/arm64/include/asm/pgtable-prot.h > @@ -79,17 +79,7 @@ extern bool arm64_use_ng_mappings; > __val; \ > }) > > -#define PAGE_S2_XN \ > - ({ \ > - u64 __val; \ > - if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) \ > - __val = 0; \ > - else \ > - __val = PTE_S2_XN; \ > - __val; \ > - }) > - > -#define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | > PTE_S2_RDONLY | PAGE_S2_XN) > +#define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | > PTE_S2_RDONLY | PTE_S2_XN) > #define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | > PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN) > > #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | > PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN) I don't understand what you are trying to achieve here. This whole point of not setting XN in the page tables when DIC is present is to avoid a pointless permission fault at run time. At you noticed above, no icache invalidation is necessary. So why would you ever want to take a fault on exec the first place? M. -- Jazz is not dead. It just smells funny...