From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4618CC4332F for ; Sat, 11 Sep 2021 02:33:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B77661211 for ; Sat, 11 Sep 2021 02:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235193AbhIKCeX (ORCPT ); Fri, 10 Sep 2021 22:34:23 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:53763 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235128AbhIKCeV (ORCPT ); Fri, 10 Sep 2021 22:34:21 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 44C92580D36; Fri, 10 Sep 2021 22:32:53 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Fri, 10 Sep 2021 22:32:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= subject:to:cc:references:from:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; s=fm3; bh=9 wn7RP7Sux9NYgDDcEExp5Udsa+3BvnVWNaKgQ+xtco=; b=C54qrA6kMQY/5XFcT HMkZjs6lh0FZRguVrhwIIxrnEospagqHftUvoYjDpwCm52GukttO6NgXCKLjCWd4 IPQ3HnUc0sspZBvEeG11N3NxPIxPAELxHPmDPkzwN3D+a7y2U4Ymnf6kKO0tEzpv /T/jlT9JM4ZHHQMfm51jRmmRJM+2NUJGu+dVVMSR/EnecBMYkKm0Ot+TNRo2fmM3 8Ss6bNrbFwpdFdmjxPq8cgRIepxZ9WZcFZMurqPQFuOCLKhn7jkwsw3i+L/oBHvd YQXYsWdsYjxJCqUVq1BUAVjMV41QYSVZ4zuYmE114hVUuAozGtptkODL8ggpSKn9 XLh9g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=9wn7RP7Sux9NYgDDcEExp5Udsa+3BvnVWNaKgQ+xt co=; b=qtYIC427B9zI8tzmC3wd15AoaBFHpEDOC4H603KsCIB0FiBofs4wkvwg7 uS9gkqjTxxsnurrBUh9uTLiFVU5y/AU2WqyvWkXFQhqXH9SSjNvCFrzXfYDv80zD Dbjd2JwpGgoW3IfzTZd41DZ0DI+/8emaVG65seFbSczgiZoiO7LGDmtkP61nGiNO q29dU+yrnOCwwDHmCcS1rC/Q004jB9wAxkp0Jvt6Aq4/6Pg9a5cQCOG0tJaXKWwm piUEidBdJvly9SUKPlltO/LYrX7RUGfolQSptC905Qh01jToxPFZNY+rO2jnFMQS 5lAtst/0U/MIehzGvTp8tBGhbfKkA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudegvddgheejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepuffvfhfhkffffgggjggtgfesthejredttdefjeenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepgfevffetleehffejueekvdekvdeitdehveegfeekheeuieeiueet uefgtedtgeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 10 Sep 2021 22:32:49 -0400 (EDT) Subject: Re: [PATCH 09/22] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support To: Paul Kocialkowski Cc: Yong Deng , Mauro Carvalho Chehab , Rob Herring , Maxime Ripard , Sakari Ailus , Hans Verkuil , Chen-Yu Tsai , Jernej Skrabec , Greg Kroah-Hartman , Helen Koike , Laurent Pinchart , Thomas Petazzoni , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev References: <20210910184147.336618-1-paul.kocialkowski@bootlin.com> <20210910184147.336618-10-paul.kocialkowski@bootlin.com> From: Samuel Holland Message-ID: <483288cb-d9fa-4581-7986-d15c4aa27769@sholland.org> Date: Fri, 10 Sep 2021 21:32:48 -0500 User-Agent: Mozilla/5.0 (X11; Linux ppc64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <20210910184147.336618-10-paul.kocialkowski@bootlin.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > controller. The controller uses a separate D-PHY, which is the same > that is otherwise used for MIPI DSI, but used in Rx mode. > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > not have access to any parallel interface pins. > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > support the MIPI CSI-2 interface. > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > even when no sensor is connected. This will result in a probe failure > for the controller as long as no sensor is connected but this is fine > since no other interface is available. > > Signed-off-by: Paul Kocialkowski > --- > arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index a77b63362a1d..ec7fa6459547 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -612,6 +612,34 @@ spi0: spi@1c68000 { > #size-cells = <0>; > }; > > + csi0: camera@1cb0000 { > + compatible = "allwinner,sun8i-v3s-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + assigned-clocks = <&ccu CLK_CSI1_SCLK>; > + assigned-clock-parents = <&ccu CLK_PLL_ISP>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csi0_in_mipi_csi2: endpoint { > + remote-endpoint = <&mipi_csi2_out_csi0>; > + }; > + }; > + }; > + }; > + > csi1: camera@1cb4000 { > compatible = "allwinner,sun8i-v3s-csi"; > reg = <0x01cb4000 0x3000>; All of the new nodes should be added above this one, to maintain unit address order. Regards, Samuel > @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { > #interrupt-cells = <3>; > interrupts = ; > }; > + > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-v3s-mipi-csi2", > + "allwinner,sun6i-a31-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + phys = <&dphy>; > + phy-names = "dphy"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + > + mipi_csi2_out_csi0: endpoint { > + remote-endpoint = <&csi0_in_mipi_csi2>; > + }; > + }; > + }; > + }; > + > + dphy: d-phy@1cb2000 { > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > + reg = <0x01cb2000 0x1000>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_MIPI_CSI>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + allwinner,direction = "rx"; > + status = "disabled"; > + #phy-cells = <0>; > + }; > }; > }; >