From: Neil Armstrong <narmstrong@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-amlogic@lists.infradead.org, jbrunet@baylibre.com
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/4] Meson8b: add the CPU clock post-dividers
Date: Fri, 23 Nov 2018 15:40:55 +0100 [thread overview]
Message-ID: <4859b354-ade4-8172-eeb5-7a4a42045589@baylibre.com> (raw)
In-Reply-To: <20181122214017.25643-1-martin.blumenstingl@googlemail.com>
On 22/11/2018 22:40, Martin Blumenstingl wrote:
> This is the successor to my previous series "meson8b: add the CPU_DIV16
> clock for the ARM TWD" from [0]. I decided to not send this as v2 of
> the original series because the PERIPH clock is not the CPU_DIV16 clock.
> It's not clear whether a CPU_DIV16 clock exists.
>
> With this series we get all the CPU_CLK post-dividers as listed in the
> public S805 datasheet [1] on pages 31 and 32:
> - ABP
> - PERIPH (used as input for the ARM global timer and ARM TWD timer)
> - AXI
> - L2 DRAM
>
> Each of these clocks has a register called "..._CLK_DIS" which is
> documented as a "just in case" bit:
> "Set to 1 to manually disable the [...] clock when changing the mux
> selection. Typically this bit is set to 0 since the clock muxes can
> switch without glitches."
> Since we're not supposed to touch that register we're using the new
> read-only gate clk_ops to ensure that nothing accidentally modifies
> these bits.
>
> The result of this is that we can use the PERIPH clock which clocks
> the ARM TWD timer. I will send a separate series to add the TWD timer.
>
>
> changes since v1 at [2]:
> - added new patch 2 "clk: meson: clk-regmap: add read-only gate ops"
> - switched from CLK_IS_CRITICAL to the new clk_regmap_gate_ro_ops
> so we're consistent with all other read-only clocks
> - collected Jerome's Acked-by tags (thanks!)
>
>
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html
> [1] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [2] https://patchwork.kernel.org/cover/10687023/
>
>
> Martin Blumenstingl (4):
> dt-bindings: clock: meson8b: export the CPU post dividers
> clk: meson: clk-regmap: add read-only gate ops
> clk: meson: meson8b: rename cpu_div2/cpu_div3 to
> cpu_in_div2/cpu_in_div3
> clk: meson: meson8b: add the CPU clock post divider clocks
>
> drivers/clk/meson/clk-regmap.c | 5 +
> drivers/clk/meson/clk-regmap.h | 1 +
> drivers/clk/meson/meson8b.c | 264 ++++++++++++++++++++++-
> drivers/clk/meson/meson8b.h | 17 +-
> include/dt-bindings/clock/meson8b-clkc.h | 4 +
> 5 files changed, 278 insertions(+), 13 deletions(-)
Applied, with the bindings on next/headers
Neil
next prev parent reply other threads:[~2018-11-23 14:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-22 21:40 [PATCH v2 0/4] Meson8b: add the CPU clock post-dividers Martin Blumenstingl
2018-11-22 21:40 ` [PATCH v2 1/4] dt-bindings: clock: meson8b: export the CPU post dividers Martin Blumenstingl
2018-11-23 15:20 ` Neil Armstrong
2018-11-22 21:40 ` [PATCH v2 2/4] clk: meson: clk-regmap: add read-only gate ops Martin Blumenstingl
2018-11-23 14:06 ` Neil Armstrong
2018-11-22 21:40 ` [PATCH v2 3/4] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 Martin Blumenstingl
2018-11-22 21:40 ` [PATCH v2 4/4] clk: meson: meson8b: add the CPU clock post divider clocks Martin Blumenstingl
2018-11-23 14:40 ` Neil Armstrong [this message]
2018-11-23 19:40 ` [PATCH v2 0/4] Meson8b: add the CPU clock post-dividers Martin Blumenstingl
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