From: Jonathan Cameron <Jonathan.Cameron@gmail.com>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Andrew Morton <akpm@osdl.org>, David Brownell <david-b@pacbell.net>
Subject: [patch 2.6.26] gpio: pcf857x handle pca9500 and pca9501
Date: Thu, 24 Jul 2008 17:08:05 +0100 [thread overview]
Message-ID: <4888A8E5.6050700@gmail.com> (raw)
From: Jonathan Cameron <jic23@cam.ac.uk>
Addition of pca9500 and pca9501 chips to the pcf857x driver.
Signed-off-by: Jonathan Cameron <jic23@cam.ac.u>
--
These two chips have two elements (on different i2c addresses), the first is a clone
of the pcf8574 and the second 2kBit eeprom. Seems easiest to support these separately
so main query about this patch is should the device naming reflect this dual
functionality.
I've been using the pcf857x driver with a 9500 for several months without problems and
just want this in to clean up a confusing element in a board config.
As the Kconfig title for these is getting a bit long and the datasheet for these starts
with stating they are pcf957x compatible so I haven't changed it.
--
diff -uprN -X a/Documentation/dontdiff a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
--- a/drivers/gpio/Kconfig 2008-07-24 16:55:57.000000000 +0100
+++ b/drivers/gpio/Kconfig 2008-07-24 16:51:45.000000000 +0100
@@ -54,6 +54,7 @@ config GPIO_PCF857X
some of them. Compatible models include:
8 bits: pcf8574, pcf8574a, pca8574, pca8574a,
+ pca9500, pca9501,
pca9670, pca9672, pca9674, pca9674a,
max7328, max7329
diff -uprN -X a/Documentation/dontdiff a/drivers/gpio/pcf857x.c b/drivers/gpio/pcf857x.c
--- a/drivers/gpio/pcf857x.c 2008-07-24 16:55:57.000000000 +0100
+++ b/drivers/gpio/pcf857x.c 2008-07-24 16:56:51.000000000 +0100
@@ -29,6 +29,8 @@
static const struct i2c_device_id pcf857x_id[] = {
{ "pcf8574", 8 },
{ "pca8574", 8 },
+ { "pca9500", 8 },
+ { "pca9501", 8 },
{ "pca9670", 8 },
{ "pca9672", 8 },
{ "pca9674", 8 },
@@ -44,9 +46,9 @@ static const struct i2c_device_id pcf857
MODULE_DEVICE_TABLE(i2c, pcf857x_id);
/*
- * The pcf857x, pca857x, and pca967x chips only expose one read and one
- * write register. Writing a "one" bit (to match the reset state) lets
- * that pin be used as an input; it's not an open-drain model, but acts
+ * The pcf857x, pca857x, pca950x and pca967x chips only expose one read
+ * and one write register. Writing a "one" bit (to match the reset state)
+ * lets that pin be used as an input; it's not an open-drain model, but acts
* a bit like one. This is described as "quasi-bidirectional"; read the
* chip documentation for details.
*
next reply other threads:[~2008-07-24 16:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-07-24 16:08 Jonathan Cameron [this message]
2008-07-25 1:17 ` [patch 2.6.26] gpio: pcf857x handle pca9500 and pca9501 David Brownell
2008-07-25 11:48 ` Jonathan Cameron
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